Abstract: A lateral DMOS transistor structure includes a substrate of a first dopant polarity, a body region of the first dopant polarity, a source region, a drift region of a second dopant polarity, a drain region, a channel region, a gate structure over the channel region, a hybrid contact implant, of the second dopant polarity, in the source region, and a respective metal contact on or within each of the source region, gate structure, and drain region. The hybrid contact implant and the metal contact together form a hybrid contact defining first, second, and third electrical junctions. The first junction is a Schottky junction formed vertically between the source metal contact and the body. The second junction is an ohmic junction formed laterally between the source metal contact and the hybrid contact implant. The third junction is a rectifying PN junction between the hybrid contact implant and the channel region.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: A semiconductor device includes an active region configured by a first MOS structure region and a second MOS structure region, a gate ring region surrounding a periphery of the active region, a first ring region surrounding a periphery of the gate ring region, a second ring region surrounding a periphery of the first ring region, and a termination region surrounding a periphery of the second ring region. The semiconductor device has first first-electrodes in the first MOS structure region, second first-electrodes in the second MOS structure region, a third first-electrode in the first ring region, and a fourth first-electrode in the second ring region. The third first-electrode has a potential equal to that of the second first-electrodes, and the fourth first-electrode has a potential equal to that of the first first-electrodes.

Abstract: A semiconductor device includes a base substrate. A first thin-film transistor is disposed on the base substrate. The first thin-film transistor includes a first input electrode, a first output electrode, a first semiconductor pattern disposed below a first insulating layer, and a first control electrode disposed on the first insulating layer and below a second insulating layer. A second thin-film transistor includes a second input electrode, a second output electrode, a second semiconductor pattern disposed on the second insulating layer, and a second control electrode disposed on an insulating pattern formed on the second semiconductor pattern and exposes a portion of the second semiconductor pattern. The first semiconductor pattern includes a crystalline semiconductor. The second semiconductor pattern includes an oxide semiconductor. The first semiconductor pattern, the first control electrode, the second semiconductor pattern, and the second control electrode are overlapped.

Abstract: A qubit includes a substrate, and a first capacitor structure having a lower portion formed on a surface of the substrate and at least one first raised portion extending above the surface of the substrate. The qubit further includes a second capacitor structure having a lower portion formed on the surface of the substrate and at least one second raised portion extending above the surface of the substrate. The first capacitor structure and the second capacitor structure are formed of a superconducting material. The qubit further includes a junction between the first capacitor structure and the second capacitor structure. The junction is disposed at a predetermined distance from the surface of the substrate and has a first end in contact with the first raised portion and a second end in contact with the second raised portion.

Abstract: Provided is a field effect transistor including a semiconductor layer, a gate electrode provided on a channel region in the semiconductor layer, and a channel adjusting member provided adjacent to the channel region on one surface of the semiconductor layer and overlapping the gate electrode on a plane. Here, the channel adjusting member provides a depletion layer in the channel region.

Abstract: A moisture and hydrogen adsorption getter is provided. The moisture and hydrogen adsorption getter includes a silicon substrate including a concave portion and a convex portion, a silicon oxide layer conformally provided along a surface of the concave portion and a surface of the convex portion and configured to adsorb moisture, and a hydrogen adsorption pattern disposed on the silicon oxide layer. A portion of the silicon oxide layer is exposed between portions of the hydrogen adsorption pattern.

Abstract: Structures for a corner area of a chip and methods of fabricating a structure for a corner area of a chip. A chip includes an active circuit region, an integrated circuit in the active circuit region, and a corner area. The corner area includes dummy structures that provide dummy fill.

Abstract: A HEMT comprises a composite channel, made up of a plurality of channel/barrier layer heterojunctions. That is, two or more channel/barrier layer pairs are deposited on a substrate, under a gate contact. A separate 2DEG is formed in each channel layer at the heterojunction with the barrier layer. The HEMT channel is effectively divided among a plurality of parallel 2DEGs. A high total charge density—required for high power operation—is divided among the plurality of 2DEGs. Since each 2DEG does not have a large charge density, it can sustain the high saturated electron velocity required for very high frequency operation. The composite-channel HEMT thus operates with high gain, at high power levels, and at high frequencies.

Abstract: A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.

Abstract: A semiconductor device, comprising a first MOS structure region, a second MOS structure region, a first temperature sensing region, and a second temperature sensing region. The first temperature sensing region is provided in a region through which a main current of the semiconductor device passes when the first MOS structure region is in an ON state. The second temperature sensing region is provided in a region through which the main current of semiconductor device passes when the second MOS structure region is in the ON state.

Abstract: An integrated circuit device includes a substrate having a first region and a second region separated from each other along a direction parallel to an upper surface of the substrate. An interface device isolation layer fills an interface trench in an interface region between the first region and the second region and defines a portion of a first active area positioned in the first region and a portion of a second active area positioned in the second region. An insulation pattern extends from the first region to an upper portion of the interface device isolation layer. The insulation pattern covers the first active area and at least a portion of the interface device isolation layer. The insulation pattern defines an undercut area on an upper surface of the interface device isolation layer. A buried pattern substantially fills the undercut region.

Abstract: A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures.

Abstract: A system for pattern-based identification of a driver of a vehicle includes a mobile device; and a server configured to communicate with the mobile device. The mobile device collects movement information during a driving trip via one or more sensors in the mobile device, and communicates the collected movement information to a server. The server analyzes the movement information via a classifier, identifies driving features for the driver based at least in part on the analysis of the movement information, creates an identification model for the driver based on identified driving features, and stores the identification model.

Abstract: A vertical JFET is provided. The JFET is mixed with lateral channel structure and p-GaN gate structure. The JFET has an improved barrier layer for p-GaN block layer and enhanced Ohmic contact with source. In one embodiment, regrowth of lateral channel is provided so that counter doping surface Mg will be buried. In another embodiment, a dielectric layer is provided to protect p-type block layer during the processing, and later make Ohmic source and p-type block layer. Method of a barrier regrown layer for enhanced lateral channel performance is provided where a regrown barrier layer is deposited over the drift layer. The barrier regrown layer is an anti-p-doping layer. Method of a patterned regrowth for enhanced Ohmic contact is provided where a patterned masked is used for the regrowth.

Abstract: A vertical-type memory device includes: a first gate structure including first gate electrodes spaced apart from each other and stacked on a substrate; first channel structures penetrating through the first gate structure and being in contact with the substrate; a second gate structure including second gate electrodes spaced apart from each other and stacked on the first gate structure; and second channel structures penetrating through the second gate structure and being in contact with the first channel structures. The first channel structures each may include a first channel layer penetrating the first gate structure, and a first channel pad disposed on the first channel layer and including a first pad region including n-type impurities and a second pad region including p-type impurities.

Abstract: A silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region having a second conductivity type, a third impurity region having the first conductivity type, and a fourth impurity region provided between a second main surface and a bottom surface and having the second conductivity type. The first impurity region has a first region being in contact with the second impurity region and having a first impurity concentration, a second region being continuous to the first region, provided between the first region and the second main surface, and having a second impurity concentration lower than the first impurity concentration, and a third region being continuous to the first region and having a third impurity concentration higher than the first impurity concentration. A side surface is in contact with the third region, the second impurity region, and the third impurity region.

Abstract: An image sensor includes one or more first unit pixels. Each of the one or more first unit pixels may include a first photoelectric conversion region including first photoelectric conversion elements arranged in the form of a matrix, and a first floating diffusion region at a center of the first photoelectric conversion elements; a first transistor region including a first active region in which a first reset gate, a first select gate and a first drive gate are disposed; a first signal interconnect electrically connecting the first floating diffusion region to the first drive gate; and a first shielding interconnect separated from the first signal interconnect and extending parallel to the first signal interconnect.

Abstract: In some embodiments, the present disclosure relates to an integrated chip including one or more lower interconnect layers arranged within one or more stacked inter-layer dielectric layers over a substrate. A bottom electrode is disposed over the one or more interconnect layers, and a top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts a first surface of the bottom electrode and a second surface of the top electrode. The ferroelectric layer includes a protrusion that extends past outer surfaces of the top electrode and the bottom electrode along a first direction that is perpendicular to a second direction that is normal to the first surface. The protrusion is confined between lines that extend along the first and second surface.

Abstract: The sense region is spaced from the active region. The isolation trench surrounds the sense region and isolates the sense region from the active region. The active region is provided with a first gate trench defined by a first side surface and a first bottom surface continuing to the first side surface. The first insulating film is in contact with both the first side surface and the first bottom surface. The first conductor is provided on the first insulating film. The second insulating film is provided in the isolation trench. The second conductor is provided on the second insulating film. The isolation trench reaches a first impurity region. The first insulating film is made of a material identical to that of the second insulating film. The first conductor is made of a material identical to that of the second conductor and is electrically isolated from the second conductor.