Abstract: A semiconductor structure includes a substrate, an isolation structure formed in the substrate, and a word line including a first convex portion and a second convex portion. The first convex portion and the second convex portion are located in the isolation structure, and a depth of the first convex portion is greater than a depth of the second convex portion.

Abstract: In a display device, a first power supply voltage line includes a first trunk wiring line, a plurality of branch wiring lines, and a second power supply voltage line includes a second trunk wiring line. The first trunk wiring line includes a first portion and a second portion. A line width of the first portion is smaller than a line width of the second portion. A frame region in a frame region provided with the first portion includes a first irregular frame edge having an irregular shape.

Abstract: A semiconductor device includes a first layer that contains gold (Au) and is formed on one surface of a semiconductor substrate and a second layer that contains nickel (Ni) and is formed on the first layer. The semiconductor device is provided with a via hole that passes through the second layer, the first layer, and the semiconductor substrate from one surface to another surface opposite thereto, and a via wiring is formed on the inner surface of the via hole. The second layer is a mask used when the semiconductor substrate is etched to form the via hole, and the first layer is a base layer for forming the second layer on the semiconductor substrate. By using an Au-containing layer as the first layer, side etching on the first layer is prevented when the semiconductor substrate is etched, and disconnection of the via wiring is prevented.

Abstract: A semiconductor device includes first and second nitride semiconductor layers. The second layer on the first nitride has a first region, a second region, and a third region between the first and second regions. A first gate electrode is in the first region and extends parallel to a surface of a substrate. A first source electrode is in the first region and extends in the first direction. A second gate electrode in the second region and extends in the first direction. A second source electrode is in the second region and extends in the first direction. A drain electrode coupled to a first and a second wiring. The first wiring directly contacts the second nitride semiconductor layer in the first region. The second wiring directly contacts the second nitride semiconductor layer in the second region. An insulation material is in the third region.

Abstract: Gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having germanium-doped nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. Individual ones of the vertical arrangement of nanowires have a relatively higher germanium concentration at a lateral mid-point of the nanowire than at lateral ends of the nanowire.

Abstract: A method for manufacturing a HEMT device includes forming, on a heterostructure, a dielectric layer, forming a through opening through the dielectric layer, and forming a gate electrode in the through opening. Forming the gate electrode includes forming a sacrificial structure, depositing by evaporation a first gate metal layer layer, carrying out a lift-off of the sacrificial structure, depositing a second gate metal layer by sputtering, and depositing a third gate metal layer. The second gate metal layer layer forms a barrier against the diffusion of metal atoms towards the heterostructure.

Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip including forming a ferroelectric layer over a bottom electrode layer, forming a top electrode layer over the ferroelectric layer, performing a first removal process to remove peripheral portions of the bottom electrode layer, the ferroelectric layer, and the top electrode layer, and performing a second removal process using a second etch that is selective to the bottom electrode layer and the top electrode layer to remove portions of the bottom electrode layer and the top electrode layer, so that after the second removal process the ferroelectric layer has a surface that protrudes past a surface of the bottom electrode layer and the top electrode layer.

Abstract: Embodiments include structures and methods for fabricating an MFM capacitor having a plurality of metal contacts. An embodiment may include a first metal strip, disposed on a substrate and extending in a first direction, a ferroelectric blanket layer, disposed on the first metal strip, a second metal strip, disposed on the ferroelectric blanket layer and extending in a second direction different from the first direction, and a plurality of metal contacts disposed between the first metal strip and the second metal strip and located within an intersection region of the first metal strip and the second metal strip.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, a first conductive member, a first electrode, a first insulating member, and a second insulating member. The semiconductor member includes a first partial region, a second partial region, and a third partial region. The first partial region is between the second partial region the third partial region. The first conductive member includes a first conductive portion. The first conductive portion is between the second partial region and the third partial region. The first electrode is electrically connected to the first conductive member. The first electrode includes a first electrode portion, a second electrode portion, and a third electrode portion. The first insulating member includes a first insulating region, a second insulating region, and a third insulating region. The second insulating member includes a first insulating portion and a second insulating portion.

Abstract: A semiconductor device includes a conductive pattern extending in a first direction, a magnetic tunnel junction pattern on the conductive pattern, and a capacitor on the magnetic tunnel junction pattern. The magnetic tunnel junction pattern is between the conductive pattern and the capacitor, and the magnetic tunnel junction pattern connects to the capacitor, and the conductive pattern is configured to apply spin-orbit torque to the magnetic tunnel junction pattern.

Abstract: A semiconductor device with enhanced semiconductor characteristics that is useful for power devices. A semiconductor device, including: an n-type semiconductor layer; one or more p-type semiconductors; an electrode, the one or more p-type semiconductors that are provided between the n-type semiconductor layer and the electrode, and at least a part of the one or more p-type semiconductors is protruded in the electrode.

Abstract: An organic light-emitting diode display device is provided by the present application, including an anode layer, a cathode layer, and a light-emitting layer disposed between the anode layer and the cathode layer, wherein the light-emitting layer includes a first light-emitting layer and a second light-emitting layer stacked. The first light-emitting layer includes a first color light-emitting part, a second color light-emitting part, and a third color light-emitting part arranged in a same layer. The second light-emitting layer is configured to emit light of a first color, and the second light-emitting layer is disposed at a side of the first light-emitting layer and covers the first light-emitting layer.

Abstract: Disclosed herein are transistors, memory cells, and arrangements thereof. For example, in some embodiments, an integrated circuit (IC) structure may include a plurality of transistors, wherein the transistors are distributed in a hexagonally packed arrangement. In another example, in some embodiments, an IC structure may include a memory cell including an axially symmetric transistor coupled to an axially symmetric capacitor, wherein the axis of the transistor is aligned with the axis of the capacitor.

Abstract: A semiconductor device includes an SiC semiconductor layer which has a first main surface on one side and a second main surface on the other side, a semiconductor element which is formed in the first main surface, a raised portion group which includes a plurality of raised portions formed at intervals from each other at the second main surface and has a first portion in which some of the raised portions among the plurality of raised portions overlap each other in a first direction view as viewed in a first direction which is one of the plane directions of the second main surface, and an electrode which is formed on the second main surface and connected to the raised portion group.

Abstract: A semiconductor device is disclosed. The semiconductor device may include a semiconductor substrate including a protruding active pattern, a first gate pattern provided on the active pattern and extended to cross the active pattern, a first capping pattern provided on a top surface of the first gate pattern, the first capping pattern having a top surface, a side surface, and a rounded edge, and a first insulating pattern covering the side surface and the edge of the first capping pattern. A thickness of the first insulating pattern on the edge of the first capping pattern is different from a thickness of the first insulating pattern on outer side surfaces of the spacer patterns.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device includes a gate electrode separated from a substrate by a gate dielectric. The gate electrode has one or more interior surfaces that form a recess within the gate electrode. A dielectric layer is disposed over the substrate and laterally surrounds the gate electrode. A dishing prevention structure is disposed within the recess. The dishing prevention structure is both vertically separated from the gate dielectric and laterally separated from the dielectric layer by the gate electrode. The dishing prevention structure continuously extends between outermost sidewalls of the dishing prevention structure as viewed along a cross-sectional view extending through a center of the recess.

Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a plurality of gate structures that are spaced apart from each other in a first direction on a substrate and extend in a second direction intersecting the first direction, and a plurality of separation patterns penetrating immediately neighboring ones of the plurality of gate structures, respectively. Each of the plurality of separation patterns separates a corresponding one of the neighboring gate structures into a pair of gate structures that are spaced apart from each other in the second direction. The plurality of separation patterns are spaced apart from and aligned with each other along the first direction.

Abstract: An imaging device includes a pixel including a photoelectric conversion region, a first transfer transistor coupled to the photoelectric conversion region, a first floating diffusion, a second floating diffusion, a second transfer transistor coupled between the first floating diffusion and the second floating diffusion to control access to the second floating diffusion, a third transfer transistor coupled to the photoelectric conversion region, a third floating diffusion coupled, a fourth floating diffusion, and a fourth transfer transistor coupled between the third floating diffusion and the fourth floating diffusion to control access to the fourth floating diffusion. The imaging device includes a first wiring layer including a first wiring connected to the second floating diffusion, a second wiring connected to the fourth floating diffusion, and a third wiring connected to ground and capacitively coupled with the first wiring and the second wiring.

Abstract: A photodetector includes: a semiconductor substrate having a first main surface and a second main surface; a first semiconductor layer that is of a first conductivity type, and is included in the semiconductor substrate and closer to the first main surface than to the second main surface; a second semiconductor layer that is of a second conductivity type different from the first conductivity type, and is included in the semiconductor substrate and interposed between the first semiconductor layer and the second main surface; a multiplication region that causes avalanche multiplication to a charge generated in the semiconductor substrate through photoelectric conversion; a circuit region disposed alongside the first semiconductor layer in a direction parallel to the first main surface; at least one isolation transistor disposed in the circuit region; and an isolation region interposed between the first semiconductor layer and the circuit region.

Abstract: A semiconductor device includes a lower memory stack disposed on a substrate and including lower gate electrodes and a lower staircase structure, an upper memory stack including upper gate electrodes and an upper staircase structure, a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure, an upper interlayer insulating layer doped with an impurity and covering the upper staircase structure and the lower interlayer insulating layer, the upper interlayer insulating layer having a doping concentration gradually increasing toward the upper staircase structure and the lower interlayer insulating layer, lower contact plugs and upper contact plugs contacting the lower gate electrodes and the upper gate electrodes, respectively.