Patents Examined by Eric Ward
  • Patent number: 10411170
    Abstract: A radiation-emitting optoelectronic device, a method for using a radiation-emitting optoelectronic device and a method for making a radiation-emitting optoelectronic device are disclosed. In an embodiment, the device includes a semiconductor chip configured to emit a primary radiation and a conversion element including a conversion material which comprises Cr and/or Ni ions and a host material and which, during operation of the device, converts the primary radiation emitted by the semiconductor chip into a secondary radiation of a wavelength between 700 nm and 2000 nm, wherein the host material comprises EAGa12O19, AyGa5O(15+y)/2, AE3Ga2O14, Ln3Ga5GeO14, Ga2O3, Ln3Ga5.5D0.5O14 or Mg4D2O9, wherein EA=Mg, Ca, Sr and/or Ba, A=Li, Na, K and/or Rb, AE=Mg, Ca, Sr and/or Ba, Ln=La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and/or Lu and D=Nb and/or Ta, and wherein y=0.9-1.9.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: September 10, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Sonja Tragl, Dominik Eisert, Stefan Lange, Nils Kaufmann, Alexander Martin, Krister Bergenek
  • Patent number: 10403612
    Abstract: A dual-sided display is disclosed, including a substrate, a first active device, a first micro light emitting device, a patterned photoresist layer, a reflective electrode, a second micro light emitting device, a protective layer, and a first conductive electrode. The first micro light emitting device is disposed on the substrate and electrically connected to the first active device. The patterned photoresist layer is disposed on the substrate and covers a portion of the first micro light emitting device. The reflective electrode covers the patterned photoresist layer and a portion of the substrate. The second micro light emitting device is disposed on the reflective electrode. The protective layer covers the reflective electrode and a portion of the second micro light emitting device. The first conductive electrode covers the protective layer and is electrically connected to the second micro light emitting device.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: September 3, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Kuo-Lung Lo, Wen-Wei Yang
  • Patent number: 10396300
    Abstract: A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the gate dielectric. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. The openings expose portions of the gate dielectric and end portions of the channel material under the patterned resist layer. Metal contacts are formed at least within the openings. The metal contacts include a portion that contacts the end portions of the channel material and the portions of the gate dielectric exposed within the openings.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventors: Shu-Jen Han, Jianshi Tang
  • Patent number: 10396103
    Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: August 27, 2019
    Assignee: International Business Machines Corporation
    Inventor: Bahman Hekmatshoartabari
  • Patent number: 10388723
    Abstract: To prevent an intermediate region from contacting a cathode electrode even if a cathode region is partially defective. There is provided a semiconductor device with a semiconductor substrate that has a field stop region where first impurities of a first conduction type are implanted, an intermediate region that is formed on a back surface side of the field stop region and where second impurities of a second conduction type are implanted, and a cathode region of the first conduction type that is formed on a back surface side of the intermediate region. In a back surface of the semiconductor substrate, a concentration of the first impurities is higher than a concentration of the second impurities.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: August 20, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroki Wakimoto, Yuichi Onozawa, Takahiro Tamura, Eri Ogawa
  • Patent number: 10388666
    Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: August 20, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Zhixin Cui, Murshed Chowdhury, Johann Alsmeier, Tong Zhang
  • Patent number: 10388833
    Abstract: A light emitting diode, the light emitting diode including: a first semiconductor layer, an active layer, a second semiconductor layer, wherein a surface of the second semiconductor layer defines a first area; a metallic plasma generating layer; a first electrode; a second electrode; wherein the metallic plasma generating layer includes a plurality of three-dimensional nanostructures, the three-dimensional nanostructure includes a first rectangular structure, a second rectangular structure, and a triangular prism structure, the first rectangular structure, the second rectangular structure, and the triangular prism structure are stacked, the width of the triangular prism structure is equal to the width of the second rectangular structure, and is greater than the width of the first rectangular structure, the first rectangular structure is a metal layer, and the triangular prism structure is a metal layer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: August 20, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10381429
    Abstract: A display device for preventing a defective drive and improving reliability is disclosed. The display device includes a substrate including a display portion and a pad portion outside the display portion, a plurality of power lines positioned on the pad portion of the substrate and extended from the display portion, a plurality of data lines positioned in parallel with the plurality of power lines and extended from the display portion, and a plurality of bridge electrodes configured to connect at least two of the plurality of power lines. Some of the plurality of power lines include a power pad electrode on at least an end of the corresponding power line, and a number of the power pad electrodes is less than a number of the power lines.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: August 13, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sunyoung Kwon, Dosung Kim, Seyoung Kim, Ryosuke Tani
  • Patent number: 10381365
    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Chandra Mouli, Sergei Koveshnikov, Dimitrios Pavlopoulos, Guangyu Huang
  • Patent number: 10374189
    Abstract: An opto-electronic element according to an exemplary embodiment of the present disclosure includes a transparent conductive layer including a first material made of a metal and a second material made of a metal halide.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: August 6, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dong Chan Kim
  • Patent number: 10374080
    Abstract: On a front surface of a semiconductor base, an n?-type drift layer, a p-type base layer, an n++-type source region, and a gate trench and a contact trench penetrating the n++-type source region and the p-type base layer and reaching the n?-type drift layer are provided. The contact trench is provided separated from the gate trench. A Schottky metal is embedded in the contact trench and forms a Schottky contact with the n?-type drift layer at a side wall of the contact trench. An ohmic metal is provided at a bottom of the contact trench and forms an ohmic contact with the n?-type drift layer.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: August 6, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Yusuke Kobayashi, Takahito Kojima, Shinsuke Harada
  • Patent number: 10366918
    Abstract: After forming source/drain contact openings to expose portions of source/drain regions composed of an n-doped III-V compound semiconductor material, surfaces of the exposed portions of the source/drain regions are cleaned to remove native oxides and doped with plasma-generated n-type dopant radicals. Semiconductor caps are formed in-situ on the cleaned surfaces of the source/drain regions, and subsequently converted into metal semiconductor alloy regions. Source/drain contacts are then formed on the metal semiconductor alloy regions and within the source/drain contact openings.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Sebastian U. Engelmann, Marinus Johannes Petrus Hopstaken, Christopher Scerbo, Hongwen Yan, Yu Zhu
  • Patent number: 10367056
    Abstract: An HVJT is includes a parasitic diode formed by pn junction between an n?-type diffusion region and a second p?-type separation region surrounding a periphery thereof. The n?-type diffusion region is arranged between an n-type diffusion region that is a high potential side region and an n-type diffusion region that is a low potential side region, and electrically separates these regions. In the n?-type diffusion region, an nchMOSFET of a level-up level shift circuit is arranged. The n?-type diffusion region has a planar layout in which the n?-type diffusion region surrounds a periphery of the n-type diffusion region and a region where the nchMOSFET is arranged protrudes inwardly. A high-concentration inter-region distance L1 of the nchMOS region where the nchMOSFET is arranged is longer than a high-concentration inter-region distance L2 of the parasitic diode. Thus, the reliability of the semiconductor device may be improved.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: July 30, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahide Tanaka, Masaharu Yamaji
  • Patent number: 10361333
    Abstract: A detector. The detector includes a first collector, a first interface layer on the first collector, a first absorber on the first interface layer, a second interface layer on the first absorber, and a second collector on the second interface layer. The first absorber is configured to absorb photons to generate electron-hole pairs. The first interface layer may include a barrier configured to impede the flow of majority carriers from the first absorber to the first collector. The second barrier may include a barrier configured to impede the flow of majority carriers from the first absorber, or from a second absorber, to the second collector.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: July 23, 2019
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Hasan Sharifi, Terence J. DeLyon
  • Patent number: 10359340
    Abstract: An energy-efficient industrial sensor is provided that optimizes power consumption based on characteristics of the requirements of the sensing application in which the sensor is used. Operating parameters of the sensor, such as sensing range, operating frequency, response time, noise immunity, or other such parameters, can be scaled to suit the sensing and response requirements and environmental conditions of the sensing application. This allows the sensor to consume less energy when used in sensing applications that do not require peak sensor performance. In some embodiments, the sensor can measure the environmental or machine operating conditions in its immediate vicinity and dynamically scale its operating parameters based on the measured information. By down-scaling the sensor's operating parameters from their maximum performance levels where appropriate, the overall energy footprint of a network of sensors can be reduced.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: July 23, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Frederic Boutaud, Suresh Nair
  • Patent number: 10355009
    Abstract: A first-tier structure including a first alternating stack of first insulating layers and first spacer material layers is formed over a substrate. First-tier memory openings and at least one type of first-tier contact openings can be formed simultaneously employing a same anisotropic etch process. The first-tier contact openings formed over stepped surfaces of the first alternating stack may extend through the first alternating stack, or may stop on the stepped surfaces. Sacrificial first-tier opening fill portions are formed in the first-tier openings, and a second-tier structure can be formed over the first-tier structure. Memory openings including volumes of the first-tier memory openings are formed through the multi-tier structure, and memory stack structures are formed in the memory openings. Various contact openings are formed through the multi-tier structure, and various contact via structures are formed in the contact openings.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 16, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Zhixin Cui, Murshed Chowdhury, Johann Alsmeier, Tong Zhang
  • Patent number: 10355211
    Abstract: A display device includes a sensing line and a data driver. The sensing line is in a display panel. The data driver includes a plurality of integrated circuits. Each of the integrated circuits includes an interface, which includes a mobile industry processor interface (MIPI) and a crack detector. The crack detector detects cracks of the panel based on the sensing line and transmits and receives information corresponding to the crack to and from adjacent ones of the integrated circuits using a transmission terminal and a reception terminal in the MIPI.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: July 16, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Ho Seok Han
  • Patent number: 10347725
    Abstract: An emitter electrode includes a first electrode layer, a second electrode layer, and a third electrode layer. The first to third electrode layers are laid in this order on an emitter layer. A solder layer is further laid on the third electrode layer. The first electrode layer covers the emitter layer and a gate oxide film in a front surface of a semiconductor chip. A first electroconductive material forming the first electrode layer has AlSi as its main component. A second electroconductive material forming the second electrode layer has a linear expansion coefficient different from that of the first electroconductive material and is lower in mechanical strength than the first electroconductive material. A third electroconductive material constituting the third electrode layer has a linear expansion coefficient different from that of the first electroconductive material and has solder wettability higher than that of the first electrode layer.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Akihiko Nobukuni, Hirofumi Oki, Yoshifumi Tomomatsu
  • Patent number: 10347667
    Abstract: A method is presented for forming a monolithically integrated semiconductor device. The method includes forming a first device including first hydrogenated silicon-based contacts formed on a first portion of a semiconductor material of an insulating substrate and forming a second device including second hydrogenated silicon-based contacts formed on a second portion of the semiconductor material of the insulating substrate. Source and drain contacts of the first device are formed before a gate contact of the first device and a gate contact of the second device is formed before the emitter and collector contacts of the second device. The first device can be a heterojunction field effect transistor (HJFET) and the second device can be a (heterojunction bipolar transistor) HBT. The HJFET and the HBT are integrated in a neuronal circuit and create negative differential resistance by forming a lambda diode.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 9, 2019
    Assignee: International Business Machines Corporation
    Inventor: Bahman Hekmatshoartabari
  • Patent number: 10347489
    Abstract: A method of manufacturing a semiconductor device is presented. The method includes providing a semiconductor layer comprising silicon carbide, wherein the semiconductor layer comprises a first region doped with a first dopant type. The method further includes implanting the semiconductor layer with a second dopant type using a single implantation mask and a substantially similar implantation dose to form a second region and a junction termination extension (JTE) in the semiconductor layer, wherein the implantation dose is in a range from about 2×1013 cm?2 to about 12×1013 cm?2. Semiconductor devices are also presented.
    Type: Grant
    Filed: July 2, 2013
    Date of Patent: July 9, 2019
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Peter Almern Losee, Alexander Viktorovich Bolotnikov, Stacey Joy Kennerly