Patents Examined by Eric Ward
  • Patent number: 12132046
    Abstract: Disclosed are semiconductor devices and methods of fabricating the same. The semiconductor device includes a plurality of gate structures that are spaced apart from each other in a first direction on a substrate and extend in a second direction intersecting the first direction, and a plurality of separation patterns penetrating immediately neighboring ones of the plurality of gate structures, respectively. Each of the plurality of separation patterns separates a corresponding one of the neighboring gate structures into a pair of gate structures that are spaced apart from each other in the second direction. The plurality of separation patterns are spaced apart from and aligned with each other along the first direction.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: October 29, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jun Kim, Beomjin Park, Dong Il Bae, Mirco Cantoro
  • Patent number: 12119360
    Abstract: An imaging device includes a pixel including a photoelectric conversion region, a first transfer transistor coupled to the photoelectric conversion region, a first floating diffusion, a second floating diffusion, a second transfer transistor coupled between the first floating diffusion and the second floating diffusion to control access to the second floating diffusion, a third transfer transistor coupled to the photoelectric conversion region, a third floating diffusion coupled, a fourth floating diffusion, and a fourth transfer transistor coupled between the third floating diffusion and the fourth floating diffusion to control access to the fourth floating diffusion. The imaging device includes a first wiring layer including a first wiring connected to the second floating diffusion, a second wiring connected to the fourth floating diffusion, and a third wiring connected to ground and capacitively coupled with the first wiring and the second wiring.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: October 15, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Frederick Brady, Adarsh Basavalingappa, Taisuke Suwa, Michiel Timmermans, Sungin Hwang
  • Patent number: 12113078
    Abstract: A photodetector includes: a semiconductor substrate having a first main surface and a second main surface; a first semiconductor layer that is of a first conductivity type, and is included in the semiconductor substrate and closer to the first main surface than to the second main surface; a second semiconductor layer that is of a second conductivity type different from the first conductivity type, and is included in the semiconductor substrate and interposed between the first semiconductor layer and the second main surface; a multiplication region that causes avalanche multiplication to a charge generated in the semiconductor substrate through photoelectric conversion; a circuit region disposed alongside the first semiconductor layer in a direction parallel to the first main surface; at least one isolation transistor disposed in the circuit region; and an isolation region interposed between the first semiconductor layer and the circuit region.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: October 8, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akito Inoue, Yuki Sugiura, Yutaka Hirose
  • Patent number: 12107049
    Abstract: A semiconductor device includes a lower memory stack disposed on a substrate and including lower gate electrodes and a lower staircase structure, an upper memory stack including upper gate electrodes and an upper staircase structure, a lower interlayer insulating layer doped with an impurity and covering the lower staircase structure, the lower interlayer insulating layer having a doping concentration gradually increasing toward the lower staircase structure, an upper interlayer insulating layer doped with an impurity and covering the upper staircase structure and the lower interlayer insulating layer, the upper interlayer insulating layer having a doping concentration gradually increasing toward the upper staircase structure and the lower interlayer insulating layer, lower contact plugs and upper contact plugs contacting the lower gate electrodes and the upper gate electrodes, respectively.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: October 1, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Younseok Choi, Byungsun Park, Youngil Lee, Jaechul Lee, Jiwoon Im
  • Patent number: 12107095
    Abstract: One object of the present invention is to provide a solid-state imaging device, a method for fabricating a solid-state imaging device, and an electronic apparatus that implement both a wide dynamic range and a high sensitivity. A storage capacitor serving as a storage capacitance element includes a first electrode and a second electrode on a second substrate surface side. The first electrode is formed of a p+ region (the second conductivity type semiconductor region) formed in the surface of a second substrate surface of a substrate, and the second electrode is formed above the second substrate surface so as to be opposed at a distance to the first electrode in the direction perpendicular to the substrate surface. The first electrode and the second electrode are arranged so as to spatially overlap with a photoelectric conversion part in the direction perpendicular to the substrate surface.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: October 1, 2024
    Assignees: BRILLNICS SINGAPORE PTE. LTD., TOHOKU TECHNO ARCH CO., LTD.
    Inventors: Shunsuke Okura, Isao Takayanagi, Kazuya Mori, Ken Miyauchi, Shigetoshi Sugawa
  • Patent number: 12107096
    Abstract: An imaging device includes a photoelectric conversion layer, a counter electrode provided above the photoelectric conversion layer, a pixel electrode that faces the counter electrode with the photoelectric conversion layer disposed between the counter electrode and the pixel electrode, and a contact plug covered with the pixel electrode and connected to the pixel electrode. The pixel electrode includes a first layer and a second layer provided on the first layer in contact with the first layer. A surface of the first layer that is in contact with the second layer has a protrusion that protrudes upward.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: October 1, 2024
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Morikazu Tsuno, Takanori Doi, Yoshinori Takami
  • Patent number: 12094978
    Abstract: An oxide semiconductor thin film transistor and a method of forming the oxide semiconductor thin film transistor are provided. The oxide semiconductor thin film transistor can include a semiconductor layer including a channel region, a source region and a drain region; a first gate insulating layer on the semiconductor layer; a gate electrode on the first gate insulating layer; a second gate insulating layer on the gate electrode; an auxiliary electrode on the second gate insulating layer; an interlayer insulating layer on the auxiliary electrode; and a source electrode and a drain electrode on the interlayer insulating layer, wherein the source region and the drain region being disposed at both sides of the channel region, wherein the gate electrode overlapping with the channel region, and the auxiliary electrode overlapping with the gate electrode.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: September 17, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Hyuk Ji, Jin Chae Jeon, Jae Hyun Kim, Sun Young Choi, Mi Jin Jeong
  • Patent number: 12094926
    Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a deep shielding pattern that may improve a reliability and/or a functioning of the device. An example method may include forming a wide band-gap semiconductor layer structure on a substrate, the semiconductor layer structure including a drift region that has a first conductivity type; forming a plurality of gate trenches in an upper portion of the semiconductor layer structure, the gate trenches spaced apart from each other, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; forming an obstruction over a portion of each gate trench that partially obscures the upper opening; and implanting dopants having a second conductivity type that is opposite the first conductivity type into the bottom surfaces of the gate trenches, where the dopants implanted into the bottom surface of the gate trenches form deep shielding patterns.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: September 17, 2024
    Assignee: Wolfspeed, Inc.
    Inventors: Daniel J. Lichtenwalner, Naeem Islam, Woongsun Kim, Sei-Hyung Ryu
  • Patent number: 12096658
    Abstract: Embodiments of the present disclosure provide a method of manufacturing a display panel and the display panel. The method of manufacturing the display panel includes providing an array substrate; forming an anode layer on the array substrate; forming a first pixel defining layer on the array substrate and the anode layer, wherein the first pixel defining layer includes a pixel opening exposing the anode layer; etching the first pixel defining layer to form a second pixel defining layer; forming a light-emitting layer covering the anode layer in an area of the pixel opening; forming a cathode layer on the light-emitting layer; and forming an encapsulation layer covering the cathode layer, the second pixel defining layer, and the array substrate.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: September 17, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD
    Inventor: Xingyong Zhang
  • Patent number: 12080760
    Abstract: An SiC semiconductor device includes an SiC semiconductor layer having a first main surface and a second main surface, a gate electrode embedded in a trench with a gate insulating layer, a source region of a first conductivity type formed in a side of the trench in a surface laver portion of the first main surface, a body region of a second conductivity type formed in a region at the second main surface side with respect to the source region in the surface layer portion of the first main surface, a drift region of the first conductivity type formed in a region at the second main surface side in the SiC semiconductor layer, and a contact region of the second conductivity type having an impurity concentration of not more than 1.0×1020 cm?3 and formed in the surface layer portion of the first main surface.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: September 3, 2024
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Masatoshi Aketa, Takui Sakaguchi, Yuichiro Nanen
  • Patent number: 12080762
    Abstract: A silicon carbide semiconductor device, including a semiconductor substrate containing silicon carbide, a bonding wire, and a surface electrode of an aluminum alloy containing silicon, the surface electrode being provided on a surface of the semiconductor substrate, and having a joint portion to which the bonding wire is bonded. The surface electrode has a plurality of silicon nodules formed therein, which include a number of the silicon nodules formed in the joint portion. One of the number of the silicon nodules is of a dendrite structure, and is included at an area percentage of at least 10% relative to a total area of the number of the silicon nodules in the joint portion.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: September 3, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Naoyuki Ohse, Makoto Utsumi
  • Patent number: 12082444
    Abstract: The present application provides a display device and a manufacturing method thereof. The display device includes a transparent display region and a main display region. The display device further includes a pixel defining layer. The pixel defining layer includes a first pixel defining layer and a second pixel defining layer. The first pixel defining layer is positioned in the transparent display region. The second pixel defining layer is positioned in the main display region. An absorbance of the first pixel defining layer is less than an absorbance of the second pixel defining layer.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: September 3, 2024
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Wanghui Guo
  • Patent number: 12080553
    Abstract: Structures and methods of forming semiconductor devices are presented in which a void-free core-shell hard mask is formed over a gate electrode. The void-free core-shell hard mask may be formed in some embodiments by forming a first liner layer over the gate electrode, forming a void-free material over the first liner layer, recessing the void-free material, and forming a second liner over the recessed void-free material.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: September 3, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ting Ko, Sung-En Lin, Chi On Chui
  • Patent number: 12068375
    Abstract: A nitride semiconductor device includes: a substrate; a first nitride semiconductor layer; a second nitride semiconductor layer; a first opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; a second opening penetrating through the second nitride semiconductor layer to the first nitride semiconductor layer; an electron transport layer and an electron supply layer provided along an inner face of each of the first opening and the second opening and above the second nitride semiconductor layer; a gate electrode; an anode electrode; a third opening penetrating through the electron supply layer and the electron transport layer to the second nitride semiconductor layer; a source electrode in the third opening; a drain electrode; and a cathode electrode. The anode electrode and the source electrode are electrically connected, and the cathode electrode and the drain electrode are electrically connected.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: August 20, 2024
    Assignee: PANASONIC HOLDINGS CORPORATION
    Inventors: Daisuke Shibata, Satoshi Tamura, Naohiro Tsurumi
  • Patent number: 12068408
    Abstract: In an embodiment, a HEMT is formed to have a main transistor having a main active area and a sense transistor having a sense active area. An embodiment may include that the main active area is isolated from the sense active area.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: August 20, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Herbert De Vleeschouwer, Jaume Roig-Guitart, Peter Moens, Mohammad Shawkat Zaman, Olivier Trescases
  • Patent number: 12068419
    Abstract: A method of using a diode device including providing a diode that includes an active region including a 525 micron thick. 10 k?-cm, n-type, float zone wafer, and operating the diode as a silicon-avalanche semiconductor switch.
    Type: Grant
    Filed: October 21, 2020
    Date of Patent: August 20, 2024
    Assignee: Soreq Nuclear Research Center
    Inventors: Amit Kesar, Gil Atar, Shoval Zoran, Doron Cohen-Elias
  • Patent number: 12057316
    Abstract: A method includes orienting a silicon carbide layer to a first crystal channel direction relative to a first ion beam and implanting phosphorous into the silicon carbide layer using the first ion beam to define a first doped region in the silicon carbide layer. A deviation angle between the first crystal channel direction and the first ion beam is less than ±1° and the first crystal channel direction comprises a <0001> direction or a <11-23> direction.
    Type: Grant
    Filed: September 16, 2021
    Date of Patent: August 6, 2024
    Assignee: Infineon Technologies AG
    Inventors: Moriz Jelinek, Paul Ellinghaus, Axel Koenig, Caspar Leendertz, Hans-Joachim Schulze, Werner Schustereder
  • Patent number: 12052851
    Abstract: An IC structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. From a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. First one of the long sides has a first stepped top-view profile. Second one of the long sides has a second stepped top-view profile. The first stepped top-view profile has more step rises than the second stepped top-view profile.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: July 30, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Gulbagh Singh, Shun-Chi Tsai, Chih-Ming Lee, Chi-Yen Lin, Kuo-Hung Lo
  • Patent number: 12040237
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The semiconductor device structure includes a spacer over a side of the gate stack. The semiconductor device structure includes a dielectric layer over the substrate. The dielectric layer has a first recess, the dielectric layer has an upper portion and a first lower portion, the upper portion is over the first recess, the first recess is between the first lower portion and the spacer, and the upper portion has a convex curved sidewall.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: July 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Heng Tsai, Chun-Sheng Liang, Pei-Lin Wu, Yi-Ren Chen, Shih-Hsun Chang
  • Patent number: 12040274
    Abstract: A microelectronic device comprises a stack structure comprising insulative structures vertically interleaved with conductive structures, first support pillar structures vertically extending through the stack structure in a first staircase region including steps defined at edges of tiers of the insulative structures and conductive structures, and second support pillar structures vertically extending through the stack structure in a second staircase region including additional steps defined at edges of additional tiers of the insulative structures and conductive structures, the second support pillar structures having a smaller cross-sectional area than the first support pillar structures. Related memory devices, electronic systems, and methods are also described.
    Type: Grant
    Filed: May 7, 2021
    Date of Patent: July 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Lingyu Kong, Lifang Xu, Indra V. Chary, Shuangqiang Luo, Sok Han Wong