Patents Examined by Erik T. K. Peterson
  • Patent number: 11121027
    Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: September 14, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Yen-Tien Lu, Xinghua Sun, Eric Chih-Fang Liu, Andrew W. Metz
  • Patent number: 11094657
    Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: August 17, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Virendra R. Jadhav, Krystyna W. Semkow, Kamalesh K. Srivastava, Brian R. Sundlof
  • Patent number: 11075320
    Abstract: A method of manufacturing a nitride semiconductor light-emitting element includes: growing an n-side superlattice layer that includes InGaN layers and GaN layers; and, after the step of growing the n-side superlattice layer, growing a light-emitting layer. The step of growing the n-side superlattice layer comprises repeating a cycle n times (n is a number of repetition), the cycle including growing one InGaN layer and growing one GaN layer. In the step of growing the n-side superlattice layer, the step of growing one GaN layer in each cycle from a first cycle to an mth cycle is performed using carrier gas that contains N2 gas and does not contain H2 gas. The step of growing one GaN layer in each cycle from a (m+1)th cycle to an nth cycle is performed using gas containing H2 gas as the carrier gas.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: July 27, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Tomoya Yamashita
  • Patent number: 10991759
    Abstract: Methods of forming a memory device having an array portion including a plurality of array transistors and a periphery region including peripheral circuit transistor structures of the memory device, where an upper surface of the periphery region and an upper surface of the array portion are planar (or nearly planar) after formation of the peripheral circuit transistor structures and a plurality of memory cells (formed over the array transistors). The method includes forming the peripheral circuit transistor structures in the periphery region, forming the plurality of array transistors in the array portion and forming a plurality of memory cells over respective vertical transistors. Structures formed by the method have planar upper surfaces of the periphery and array regions.
    Type: Grant
    Filed: April 25, 2017
    Date of Patent: April 27, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Sanh D. Tang, David H. Wells
  • Patent number: 10985197
    Abstract: An imaging device includes: a semiconductor substrate including a first diffusion region of a first conductivity type and a second diffusion region of the first conductivity type; a first plug that is connected to the first diffusion region and that contains a semiconductor; a second plug that is connected to the second diffusion region and that contains a semiconductor; and a photoelectric converter that is electrically connected to the first plug. An area of the second plug is larger than an area of the first plug in a plan view.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 20, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Yoshihiro Sato, Yoshinori Takami, Ryota Sakaida
  • Patent number: 10978610
    Abstract: A method of manufacturing a nitride semiconductor light-emitting element includes growing an n-side semiconductor layer, an active layer, and a p-side semiconductor layer. The step of growing the active layer includes growing a first barrier layer before growing a well layer. The step of growing the first barrier layer includes a first stage where a first nitride semiconductor layer containing In is grown with a first concentration of n-type impurity, a second stage where a second nitride semiconductor layer containing In is grown with a second concentration of n-type impurity higher than the first concentration, a third stage where a third nitride semiconductor layer containing In is grown with a third concentration of n-type impurity lower than the second concentration, and a fourth stage where a fourth nitride semiconductor layer is grown under a growth condition in which an amount of an impurity source gas is decreased or stopped.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: April 13, 2021
    Assignee: NICHIA CORPORATION
    Inventor: Takuya Okada
  • Patent number: 10974958
    Abstract: A method for producing micromechanical components is provided. A liquid starting material which can be cured by means of irradiation is applied onto a substrate. A partial volume of the starting material is cured by means of a local irradiation process using a first radiation source in order to produce at least one three-dimensional structure. The three-dimensional structure delimits at least one closed cavity in which at least one part of the liquid starting material is enclosed. Alternatively or in addition, a micromechanical component is provided that contains a liquid starting material, which is partly cured by means of irradiation, and at least one cavity in which the liquid starting material is enclosed.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: April 13, 2021
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FĂ–RDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Felix Schiebel, Christoph Eberl, Matthew Berwind, Peter Gumbsch
  • Patent number: 10900953
    Abstract: Embodiments of the invention include a method for fabricating a semiconductor device, the resulting structure, and a method for using the resulting structure. A substrate is provided. A hard mask layer is patterned over at least a portion of the substrate. Regions of the substrate not protected by the hard mask are doped to form a source region and a drain region. The hard mask layer is removed. A dielectric layer is deposited on the substrate. An insulative layer is deposited on the dielectric layer. A nano-channel is created by etching a portion of the insulative layer which passes over the source region and the drain region.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10903328
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in the substrate; removing part of the STI to form a trench in a substrate; forming an amorphous silicon layer in the trench and on the STI; performing an oxidation process to transform the amorphous silicon layer into a silicon dioxide layer; and forming a barrier layer and a conductive layer in the trench.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: January 26, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Chun Chen, Chia-Lung Chang, Yi-Wei Chen, Wei-Hsin Liu, Han-Yung Tsai
  • Patent number: 10892384
    Abstract: Etched trenches in a bond material for die singulation, and associated systems and methods are disclosed. A method for solid state transducer device singulation in accordance with one embodiment includes forming a plurality of trenches by etching through a metallic bond material forming a bond between a carrier substrate and a plurality of the dies and singulating the carrier substrate along the trenches to separate the dies. In particular embodiments, the trenches extend into the carrier substrate. In further particular embodiments, the dies are at least partially, encapsulated in a dielectric material.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Vladimir Odnoblyudov, Scott D. Schellhammer, Jeremy S. Frei
  • Patent number: 10886220
    Abstract: For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 5, 2021
    Assignee: SOCIONEXT INC.
    Inventors: Chika Ito, Isaya Sobue
  • Patent number: 10868224
    Abstract: Embodiments of the invention include a semiconductor structure comprising a light emitting layer. The semiconductor structure is attached to a support such that the semiconductor structure and the support are mechanically self-supporting. A wavelength converting material extends over the sides of the semiconductor structure and the support, wherein the wavelength converting material has a substantially uniform thickness over the top and sides of the semiconductor structure and the support.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: December 15, 2020
    Assignee: Lumileds LLC
    Inventor: Serge Joel Armand Bierhuizen
  • Patent number: 10818854
    Abstract: In a flexible organic light-emitting display device according to the present disclosure, an organic sealing film having a refractive index at least 0.3 smaller than a refractive index of each of first and second inorganic sealing films is disposed between the first and second inorganic sealing films, and, at the same time, a thickness of a front sealing layer is optimized to be less than 10 micrometers inclusive. Thus, the refractive index difference between the organic capping layer and the inorganic capping layer may be maximized to increase the micro-cavity effect. Further, by increasing the refractive index difference and optimizing the thickness in the front sealing layer, the micro-cavity effect may further be increased and, hence, the light extraction efficiency may be maximized.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: October 27, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Jinho Park, Sanggun Lee, Donghyeok Lim
  • Patent number: 10770290
    Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Tung Ying Lee, Shao-Ming Yu
  • Patent number: 10763390
    Abstract: An optical device wafer processing method for dividing an optical device wafer along a plurality of division lines to obtain a plurality of individual device chips includes applying a laser beam to a wafer substrate along each division line to thereby form a laser processed groove along each division line, and next forming a V groove along each laser processed groove on the optical device wafer by using a cutting blade having a V-shaped tip in the condition where each laser processed groove is removed by the cutting blade. A crack is formed so as to extend from the bottom of each laser processed groove due to a load applied from the cutting blade, thereby dividing the optical device wafer into the individual device chips. The depth of each laser processed groove is set smaller than the depth of cut by the cutting blade.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: September 1, 2020
    Assignee: DISCO CORPORATION
    Inventor: Takashi Okamura
  • Patent number: 10741447
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: August 11, 2020
    Assignee: Plasma-Therm LLC
    Inventors: Linnell Martinez, David Pays-Volard, Chris Johnson, David Johnson, Russell Westerman, Gordon M. Grivna
  • Patent number: 10720597
    Abstract: An electroluminescent display device includes: a substrate including a subpixel; a thin film transistor disposed at the subpixel; an overcoat layer disposed on the thin film transistor; a first electrode disposed on the overcoat layer and electrically connected to the thin film transistor; a bank layer disposed on the overcoat layer and the first electrode, the bank layer including a plurality of openings configured to expose the first electrode and a plurality of opening patterns formed in a bar shape to expose the first electrode and connect the plurality of openings; an emitting layer disposed on the first electrode and the bank layer; and a second electrode disposed on the emitting layer.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: July 21, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Yong-Hoon Choi, Keum-Kyu Min, Won-Hoe Koo
  • Patent number: 10707060
    Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a cover ring disposed above the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: July 7, 2020
    Assignee: Plasma-Therm LLC
    Inventors: Chris Johnson, David Johnson, Linnell Martinez, David Pays-Volard, Rich Gauldin, Russell Westerman, Gordon M. Grivna
  • Patent number: 10678076
    Abstract: An apparatus for treating pixels or regions of a display panel includes a measuring device configured to measure a parameter of light emitted by one or more pixels of each region of the display panel. The apparatus includes a parameter comparator operably coupled to the measuring device and configured to select one or more pixels or one or more regions of the display panel such that the measured parameter of light emitted by the one or more pixels or the one or more regions exceeds a threshold value. The apparatus also includes a laser device configured to emit a laser beam onto the selected one or more pixels or the selected one or more regions.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: June 9, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Simon Hallam, Ye Yin, Evan M. Richards, Shizhe Shen
  • Patent number: 10636907
    Abstract: Embodiments of the invention include a non-planar transistor with a strained channel and methods of forming such a transistor. In an embodiment, the non-planar transistor may include a semiconductor substrate. According to an embodiment, a first source/drain (S/D) region and a second S/D region may be formed over the semiconductor substrate and separated from each other by a channel region. A gate stack may be formed over the channel region. In order to increase the amount of strain that may be induced in the channel region, embodiments may include forming a strain enhancement opening in the semiconductor substrate that removes at least a portion of the semiconductor substrate from below the channel region.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: April 28, 2020
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Stephen M. Cea, Rishabh Mehandru, Patrick Morrow, Patrick H. Keys