Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises etching a patterned interconnect stack for form first conductive lines and expose a top surface of a first etch stop layer; etching the first etch stop layer to form second conductive lines and expose a top surface of a barrier layer; and forming a self-aligned via.

Abstract: A pick-up device 10 for picking up a semiconductor chip 100 attached to a front surface of a sheet material 110 is provided with: a stage 12 that includes a material a part or the entirety of which is capable of transmitting a destaticizing electromagnetic wave having an ionization effect and that attracts and holds a rear surface of the sheet material 110; a jacking-up pin 26 for jacking up the semiconductor chip 100 from the rear side of the stage 12; and a destaticizing mechanism 20 that destaticizes charge generated between the semiconductor chip 100 and the sheet material 110 by irradiating the rear surface of the semiconductor chip 100 with the destaticizing electromagnetic wave that is made to pass through the sheet material 110 from the rear side of the stage 12.

Abstract: A method of processing a workpiece includes sticking an adhesive layer side of a resin sheet having a layered structure that includes an adhesive layer and a base material layer, to an annular frame having an opening in covering relation to the opening, forming surface irregularities on a face side of the base material layer that is opposite the adhesive layer, placing the face side of the workpiece and the face side of the base material layer in facing relation to each other and pressing the workpiece against the resin sheet or pressing the resin sheet against the workpiece, thereby bringing the workpiece into intimate contact with the resin sheet to fix the workpiece to the resin sheet, holding the face side of the workpiece fixed to the resin sheet on a holding surface of a chuck table, and grinding the reverse side of the workpiece with a grinding stone.

Abstract: The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma source adjacent to the wall of the process chamber; providing a work piece support within the process chamber; placing the substrate onto a support film on a frame to form a work piece work piece; loading the work piece onto the work piece support; providing a clamping electrode for electrostatically clamping the work piece to the work piece support; providing a mechanical partition between the plasma source and the work piece; generating a plasma through the plasma source; and etching the work piece through the generated plasma.

Abstract: An integrated circuit process includes the following steps. A substrate including a first area and a second area is provided. A plurality of line patterns cover the substrate of the first area, and a sacrificial line pattern covers the substrate of the second area, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern. The present invention also provides an integrated circuit formed by said process. A substrate includes a first area and a second area; a plurality of line patterns cover the substrate of the first area; a slot pattern is in the substrate of the second area, wherein these line patterns are orthogonal to the slot pattern. Additionally, a plurality of line patterns cover the substrate; a sacrificial line pattern is at ends of the line patterns, wherein these line patterns separate from and are orthogonal to the sacrificial line pattern.

Abstract: A method includes epitaxially growing a first III-V compound layer over a semiconductive substrate. A second III-V compound layer is epitaxially grown over the first III-V compound layer. A source/drain contact is formed over the second III-V compound layer. A gate structure is formed over the second III-V compound layer. A pattern is formed shielding the gate structure and the source/drain contact, in which a portion of the second III-V compound layer is free from coverage by the pattern.

Abstract: A semiconductor device includes: semiconductor elements and; a lead frame including a mount having an upper surface over which the semiconductor elements and are mounted; a sealing resin sealing the lead frame and the semiconductor elements and so that outer leads and of the lead frame protrude outwardly; and a resin wall located on an inner lead between the outer lead and the mount of the lead frame. A vertical thickness of the resin wall is greater than a vertical thickness from a lower surface of the sealing resin to a lower end of the lead frame.

Abstract: An electronic device includes a semiconductor memory. The semiconductor memory may include a plurality of row lines, a plurality of column lines intersecting the row lines, and a plurality of memory cells disposed at respective intersections of the row lines and the column lines. Each memory cell includes a variable resistance pattern having an upper surface which is rounded.

Abstract: Methods and apparatus for producing a reduced contact resistance for cobalt-titanium structures. In some embodiments, a method comprises depositing a titanium layer using a chemical vapor deposition (CVD) process, depositing a titanium nitride layer on the titanium layer using an atomic layer deposition (ALD) process, depositing a first cobalt layer on the titanium nitride layer using a physical vapor deposition (PVD) process, and depositing a second cobalt layer on the first cobalt layer using a CVD process.

Abstract: There is provided a method of performing a surface processing on a substrate having a metal layer formed on a bottom portion of a recess formed in an insulating film, the method including: supplying a halogen-containing gas into a processing chamber in which the substrate is loaded; and removing a metal oxide from the bottom portion of the recess using the halogen-containing gas.

Abstract: A three-dimensional nonvolatile memory device and a method for fabricating the same include a semiconductor substrate, a plurality of active pillars, a plurality of gate electrodes, and a plurality of supporters. The semiconductor substrate includes a memory cell region and a contact region. The active pillars extend in the memory cell region perpendicularly to the semiconductor substrate. The gate electrodes intersect the active pillars, extend from the memory cell region to the contact region and are stacked on the semiconductor substrate. The supporters extend in the contact region perpendicularly to the semiconductor substrate to penetrate at least one or more of the gate electrodes.

Abstract: An array of semiconductor fins is formed on a top surface of a substrate. A dielectric material liner is formed on the surfaces of the array of semiconductor fins. A photoresist layer is applied and patterned such that sidewalls of an opening in the photoresist layer are parallel to the lengthwise direction of the semiconductor fins, and are asymmetrically laterally offset from a lengthwise direction passing through the center of mass of a semiconductor fin to be subsequently removed. An angled ion implantation is performed to convert a top portion of dielectric material liner into a compound material portion. The compound material portion is removed selective to the remaining dielectric material liner, and the physically exposed semiconductor fin can be removed by an etch or converted into a dielectric material portion by a conversion process. The dielectric material liner can be removed after removal of the semiconductor fin.

Abstract: A pattern design for defect inspection, the pattern design including a first floating conductive line; a second floating conductive line; and a grounded conductive line disposed between the first floating conductive line and the second floating conductive line. The first floating conductive line, the second floating conductive line, and the grounded conductive line are divided into a main pad region, a plurality of subregions, a plurality of sub-pad regions, and a ground region. The main pad region is positioned at a first end portion of the pattern design. The ground region is positioned at a second end portion of the pattern design. The plurality of subregions and the plurality of sub-pad regions are positioned between the main pad region and the ground region.

Abstract: A method of manufacturing a flexible display apparatus includes: preparing a substrate; forming a first charge adhesive layer having a first charge on the substrate; forming a second charge adhesive layer having a second charge, which is opposite to the first charge, on the first charge adhesive layer; forming a first charge adhesive pattern and a second charge adhesive pattern by removing an edge of each of the first charge adhesive layer and the second charge adhesive layer; forming a flexible substrate on the substrate on which the first charge adhesive pattern and the second charge adhesive pattern are formed; forming a display unit on the flexible substrate; cutting the substrate, the first charge adhesive pattern, the second charge adhesive pattern, the flexible substrate, and the display unit along a cutting line; and separating the substrate and the flexible substrate.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract: A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Abstract: A semiconductor device includes a monocrystalline substrate configured to form a channel region between two recesses in the substrate. A gate conductor is formed on a passivation layer over the channel region. Dielectric pads are formed in a bottom of the recesses and configured to prevent leakage to the substrate. Source and drain regions are formed in the recesses on the dielectric pads from a deposited non-crystalline n-type material with the source and drain regions making contact with the channel region.

Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.

Abstract: A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Abstract: Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structures are disclosed. The method includes forming a Micro-Electro-Mechanical System (MEMS) beam structure by venting both tungsten material and silicon material above and below the MEMS beam to form an upper cavity above the MEMS beam and a lower cavity structure below the MEMS beam.