Abstract: A light-emitting device manufacturing method comprises the steps of irradiating a substrate 2 having a III-V compound semiconductor layer 17 formed on a front face 2a with laser light L1 along lines to cut 5a, 5b, while locating a converging point P1 within the sapphire substrate 2 and using a rear face 2b thereof as a laser light entrance surface, and thereby forming modified regions 7a, 7b along the lines 5a, 5b within the substrate 2; then forming a light-reflecting layer on the rear face 2b of the substrate 2; and thereafter extending fractures generated from the modified regions 7a, 7b acting as a start point in the thickness direction of the substrate 2, and thereby cutting the substrate 2, the semiconductor layer 17 and the light-reflecting layer along the lines 5a, 5b, and manufacturing a light-emitting device.

Abstract: A method is provided for fabricating a finFET device. Multiple fin structures are formed over a BOX layer, and a gate stack is formed on the BOX layer. The fin structures each include a semiconductor layer and extend in a first direction, and the gate stack is formed over the fin structures and extends in a second direction. The gate stack includes dielectric and polysilicon layers. Gate spacers are formed on vertical sidewalls of the gate stack, and an epi layer is deposited over the fin structures. Ions are implanted to form source and drain regions, and the gate spacers are etched so that their upper surface is below an upper surface of the gate stack. After etching the gate spacers, silicidation is performed to fully silicide the polysilicon layer of the gate stack and to form silicide regions in an upper surface of the source and drain regions.

Abstract: A method of manufacturing a semiconductor device, which includes forming a resist layer on a substrate, performing an exposure and development process on the resist layer to form a resist pattern, performing a slimming process to slim the resist pattern, forming a mask material layer on side walls of the slimmed resist pattern, and removing the slimmed resist pattern. The slimming process further includes coating an extensive agent on the substrate, expanding the expansive agent, and removing the expanded expansive agent.

Abstract: A method for manufacturing a CMOS FET comprises forming a first interfacial SiO2 layer on a semiconductor substrate after formation a conventional dielectric isolation; forming a stack a first high-K gate dielectric/a first metal gate; depositing a first hard mask; patterning the first hard mask by lithography and etching; etching the portions of the first metal gate and the first high-K gate dielectric that are not covered by the first hard mask. A second interfacial SiO2 layer and a stack of a second high-K gate dielectric/a second metal gate are then formed; a second hard mask is deposited and patterned by lithograph and etching; the portions of the second metal gate and the second high-K gate dielectric that are not covered by the second hard mask are etched to expose the first hard mask on the first metal gate.

Abstract: This invention discloses a semiconductor device and its manufacturing method. According to the method, a stop layer is deposited on a step-shaped bottom electrode, and then a first insulating layer is deposited through a high aspect ratio process. A first chemical mechanical polishing is performed until the stop layer. A second chemical mechanical polishing is then performed to remove the upper horizontal portion of the bottom electrode. Then, a phase-change material can be formed on the vertical portion of the bottom electrode to form a phase-change element. Through arranging a stop layer, the chemical mechanical polishing process is divided into two stages. Thus, during the second chemical mechanical polishing process preformed on the bottom electrode, polishing process can be precisely controlled to avoid the unnecessary loss of the bottom electrode.

Abstract: Semiconductor devices and methods for manufacturing the same are disclosed. In one embodiment, the semiconductor device comprises a semiconductor substrate; an insulating layer located on the semiconductor substrate; a semiconductor body located on the insulating layer; a cavity formed in the semiconductor body and into the insulating layer; source/drain regions abutting opposite first side faces of the semiconductor body; gates located on opposite second side faces of the semiconductor body; a channel layer interposed between the respective second side faces and the cavity; and a super-steep-retrograded-well and a halo super-steep-retrograded-well formed in the channel layer. The super-steep-retrograded-well and the halo super-steep-retrograded-well have opposite dopant polarities.

Abstract: The present invention belongs to the technical field of semiconductor materials and specifically relates to a method for cleaning and passivizing gallium arsenide (GaAs) surface autologous oxide and depositing an Al2O3 dielectric. This method includes: use a new-type of sulfur passivant to react with the autologous oxide on the GaAs surface to clean it and generate a passive sulfide film to separate the GaAs from the outside environment, thus preventing the GaAs from oxidizing again; further cleaning the residuals such as autologous oxides and sulfides on the GaAs surface through the pretreatment reaction of the reaction source trimethyl aluminum (TMA) of the Al2O3 ALD with the GaAs surface, and then deposit high-quality Al2O3 dielectric through ALD as the gate dielectric which fully separates the GaAs from the outside environment. The present invention features a simple process and good effects, and can provide preconditions for manufacturing the GaAs devices.