Abstract: According to one embodiment, a part of a buried insulating film buried in a trench is removed; accordingly, an air gap is formed between adjacent floating gate electrodes in a word line direction, and the air gap is formed continuously along the trench in a manner of sinking below a control gate electrode.

Abstract: Disclosed are a method to fabricate a semiconductor device having a two-layered gate structure, and so fabricated a semiconductor. The gate threshold voltage can be tuned by using two metal layers with different workfunctions, disposed over a fin structure on a substrate and extending in parallel to the current flow direction in the fin structure, and by varying individual thicknesses of the layer so as to change the relative coverage of the fin structure by the layers. The method may comprise providing a substrate having a fin structure, depositing first and second gate metals, and forming a gate dielectric layer. The method may further comprise determining the workfunctions of the first and second gate metals and their thicknesses to achieve a desired gate threshold voltage. Forming the first and second gate metal layers and the dielectric layer may use processes such as deposition, epitaxial growth, CMP, or selective etching.

Abstract: The chip stack of semiconductor chips with enhanced cooling apparatus includes a first chip with circuitry on a first side and a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The apparatus further includes a thermal interface material pad placed between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip. The method includes creating a first chip with circuitry on a first side and creating a second chip electrically and mechanically coupled to the first chip by a grid of connectors. The method further includes placing a thermal interface material pad between the first chip and the second chip, wherein the thermal interface material pad includes nanofibers aligned parallel to mating surfaces of the first chip and the second chip.

Abstract: A semiconductor device package is provided with integrated antenna for wireless applications. The semiconductor device package comprises a substrate including a semiconductor chip mounted thereon; a protective layer covering the semiconductor chip; a metal pattern mounted on the protective layer; and a first connective member connecting the semiconductor chip and the metal pattern. According to this configuration, the semiconductor device package is capable of being easily manufactured while minimizing the electrical distance between the metal pattern for use as an antenna and the semiconductor chip.

Abstract: A MISFET-type hydrogen gas sensor having low power consumption which can be operated for one year or longer at a low voltage power source (for example, 1.5 to 3 V) is achieved. A sensor FET is formed in a MEMS region 34 where a Si substrate 22 of a SOI substrate is bored, and a heater wiring 32 is arranged so as to be folded between a Pi-Ti—O gate 28 and a source electrode 31S of the sensor FET and between the Pt—Ti—O gate 28 and a drain electrode 31D thereof, respectively. Further, a plurality of through-holes 36 obtained by removing a protective film so as to expose an embedded insulation layer of the SOI substrate are formed in a region where an intrinsic FET region 35 where the sensor FET is formed does not overlap with the MEMS region 34 and except for bridge regions 90, 90S, 90G, and 90H where lead-out wirings 20S, 20D, 20G, and 20H are formed and except for reinforced regions 91.

Abstract: A semiconductor structure including expanded source/drain regions that extend in an opposite direction of a gate electrode is provided. The semiconductor structure includes a stack of a body-containing region and a buried insulator portion, a gate dielectric in contact with a surface of the body-containing region, a gate electrode in contact with the gate dielectric, and a source region and a drain region laterally spaced by, and in contact with, the stack. The semiconductor structure further includes a contact level dielectric layer deposited on surfaces of the source region, the drain region and the buried insulator portion.

Abstract: According to one embodiment, a semiconductor substrate, a redistribution trace, and a surface layer are provided, with the surface layer provided on the redistribution trace. On the semiconductor substrate, a wire and a pad electrode are formed. The redistribution trace is formed on the semiconductor substrate. The surface layer is larger in width than the redistribution trace, and extends beyond the edge of the redistribution trace.

Abstract: An approach for providing a latch-up robust silicon control rectifier (SCR) is disclosed. Embodiments include providing a first N+ region and a first P+ region in a substrate for a SCR; providing first and second n-well regions in the substrate proximate the first N+ and P+ regions; providing a second N+ region in the first n-well region, and a second P+ region in the second n-well region; and coupling the first N+ and P+ regions to a ground rail, the second N+ region to a power rail, and the second P+ region to an I/O pad.

Abstract: Fin-defining mask structures are formed over a semiconductor material layer having a first semiconductor material and a disposable gate structure is formed thereupon. A gate spacer is formed around the disposable gate structure and physically exposed portions of the fin-defining mask structures are subsequently removed. The semiconductor material layer is recessed employing the disposable gate structure and the gate spacer as an etch mask to form recessed semiconductor material portions. Embedded planar source/drain stressors are formed on the recessed semiconductor material portions by selective deposition of a second semiconductor material having a different lattice constant than the first semiconductor material. After formation of a planarization dielectric layer, the disposable gate structure is removed. A plurality of semiconductor fins are formed employing the fin-defining mask structures as an etch mask. A replacement gate structure is formed on the plurality of semiconductor fins.

Abstract: An electronic MEMS device is formed by a chip having with a main face and bonded to a support via an adhesive layer. A cavity extends inside the chip from its main face and is closed by a flexible film covering the main face of the chip at least in the area of the cavity. The support has a depressed portion facing the cavity and delimited by a protruding portion facing the main face of the chip. Inside the depressed portion, the adhesive layer has a greater thickness than the projecting portion so as to be able to absorb any swelling of the flexible film as a result of the expansion of the gas contained inside the cavity during thermal processes.

Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.

Abstract: Disclosed herein is a power module package, including: a first substrate having first semiconductor chips mounted thereon; and a second substrate having second semiconductor chips mounted thereon, the second substrate being coupled with the first substrate such that a side surface in a thickness direction thereof is disposed on an upper surface of the first substrate.

Abstract: A multi-LED package includes a heat sink including a primary slug and a secondary slug separated from each other, a primary LED chip mounted on the primary slug, one or more secondary LED chips mounted on the secondary slug, a lead frame structure electrically wired to the primary and secondary LED chips, and a phosphor covering at least a part of the primary LED chip. Another multi-LED package includes a heat sink having an upper surface and partitions protruding therefrom, a primary LED chip mounted inside the partitions, one or more secondary LED chips mounted outside the partitions, a lead frame structure electrically wired to the primary and secondary LED chips, and a phosphor covering at least a part of the primary LED chip.

Abstract: A wafer level light-emitting device package may include a polymer layer that bonds a light-emitting structure to a package substrate, and the polymer layer and the package substrate may include a plurality of via holes. Also, a method of manufacturing the wafer level light-emitting device package may include forming the polymer layer on the light-emitting structure, bonding the package substrate onto the polymer layer by applying heat and pressure, and forming a plurality of via holes in the polymer layer and the package substrate.

Abstract: A direct wafer bonding process for joining GaN and silicon substrates involves pre-treating each of the wafers in an ammonia plasma in order to render the respective contact surfaces ammophilic. The GaN substrate and the silicon substrate may each comprise single crystal wafers. The resulting hybrid semiconductor structure can be used to form high quality, low cost LEDs.

Abstract: A non-volatile memory device includes first wiring structures elongated in a first direction and separated by a first gap region in a second direction, the first gap region comprising first dielectric material formed in a first process, second wiring structures elongated in a second direction and separated by a second gap region in a first direction, the second gap region comprising second dielectric material formed in a second process, and a resistive switching devices comprising active conductive material, resistive switching material, and a junction material, wherein resistive switching devices are formed at intersections of the first wiring structures and the second wiring structures, wherein the junction material comprising p+ polysilicon material overlying the first wiring material, wherein some resistive switching devices are separated by the first gap region and some resistive switching devices separated by the second gap region.

Abstract: A method of forming a capacitor structure comprises: forming a doped polysilicon layer on an underlying dielectric layer; forming a dielectric stack on the doped polysilicon layer; forming a contact hole in the dielectric stack to expose a surface region of the doped polysilicon layer; forming a conductive contact plug that fills the contact hole and is in contact with the exposed surface of the doped polysilicon layer; forming a plurality of trenches in the dielectric stack such that each trench exposes a corresponding surface region of the doped polysilicon layer; forming a conductive bottom capacitor plate on exposed surfaces of the of the dielectric stack and on exposed surfaces of the doped polysilicon layer; forming a capacitor dielectric layer on the bottom capacitor plate; and forming a conductive top capacitor plate on the capacitor dielectric layer.