Abstract: A testing assembly for an electric package is suitable for electric testing of an electric package. The electric package has many contacts on a contact surface of the electric package. The contacts are arranged along an alignment line. The testing assembly for an electric package includes a testing board and a testing socket. The testing board has many testing pads. The testing socket is mounted on the testing board. The testing socket includes an insulating body and a plurality of pins. The insulating body has a carrying surface suitable for supporting a contact surface of the electric package. The pins passing through the insulating body are served as electric channels between the contacts and the testing pads. The pins are in contact with the contacts respectively, and the adjacent pins are arranged in a staggered way or arranged in different pitches.

Abstract: A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (?m).

Abstract: Method for dynamically compensating probe tip misalignment with a semiconductor wafer. The wafer is located on a handler and the wafer is adjusted to a first temperature. Probe tips of an inspection system are moved to a first position centered above pads of a test module on the wafer. The first position is recorded in a memory of the inspection system at the first temperature. The wafer and the probe tips are adjusted to a second temperature while the wafer remains in the inspection system. A second position of the probe tips is recorded in the memory while the probe tips and the wafer are equilibrated at the second temperature. A difference between the first and second position is calculated. Relative positions of the probe tips or the wafer is compensated based on the calculated difference, such that the probe tips are re-centered above the pads at the second temperature.

Abstract: An object of the invention is to implement an IC tester wherein an analog test module can be provided at a test head while maintaining flexibility of the test head. The IC tester comprises an analog test module for testing an analog signal against the device under test. The analog test module comprises a main substrate, connected to the device under test, a first sub-substrate connected to the main substrate, the first sub-substrate comprising first analog circuits and first digital circuits electrically connected to the first analog circuits, wherein an analog test is conducted by the first analog circuits, and the first digital circuits, and a second sub-substrate connected to the main substrate, the second sub-substrate comprising second analog circuits and second digital circuits electrically connected to the second analog circuits, wherein an analog test is conducted by the second analog circuits, and the second digital circuits.

Abstract: An electrical spring probe has an elongated contact and a helical spring. The spring probe is mounted in a through hole of a non-conductive substrate. The elongated contact includes a head with a V-slot groove for engaging a solder ball lead of an IC package, a shoulder providing a surface to retain a helical spring and a beam for providing a short contact path through the spring. The helical spring is disposed about the contact, with contiguous coils on each end. The upper end of the spring is secured to the contact shoulder immediately under the head. The middle coils of the spring have a larger diameter than the contiguous coils on either end to retain the spring probe assembly in the non-conductive substrate. The bottom end of the helical spring has contiguous coils some of which extend below the substrate surface to make electrical contact with a printed circuit board. The bottom contiguous coils are of a reduced diameter and have a center axis offset from the main axis of the spring probe assembly.

Abstract: A temperature control device that includes a miniature liquid-cooled heat sink with integral heater and sensing elements is used as part of a system to provide a controlled temperature surface to an electronic device, such as a semiconductor device, during the testing phase. The temperature control device includes an interface surface configured to provide a thermal path from the device to a device under test. One such device has a liquid-cooled heat sink comprising a first heat transfer portion in a first plane and a second heat transfer portion in a second plane. The first and second heat transfer portions establish a three-dimensional cross-flow of coolant within the heat sink structure. An alternate embodiment includes parallel fluid conduits, each having a three-dimensional microchannel structure that directs coolant flow in three dimensions within the fluid conduits.

Abstract: An apparatus for detecting an electronic device testing socket including a testing base, a detecting circuit board, a depth gauge, and a conductive pressing block is provided. The detecting circuit board disposed on the testing base has a carrying surface for carrying an electronic device testing socket. The electronic device testing socket includes a plurality of pin units, and each of the pin units includes an S-shaped pin and a pair of elastic rods accommodated within recesses thereof. The depth gauge disposed on the testing base presses against a top surface of the conductive pressing block, and presses with a bottom surface thereof against the electronic device testing socket. The depth gauge is adapted to adjust a distance between the top surface of the conductive pressing block and the carrying surface. The detecting circuit board is electrically connected to the pin units for detecting the status of the pin units.

Abstract: Apparatus and methods provide built-in testing enhancements in integrated circuits. These testing enhancements permit, for example, continuity testing to pads and/or leakage current testing for more than one pad. The disclosed techniques may permit more thorough testing of integrated circuits at the die level, thereby reducing the number of defective devices that are further processed, saving both time and money. In one embodiment, a test signal is routed in real time through a built-in path that includes an input buffer for a pad under test. This permits testing of continuity between the pad and the input buffer. An output buffer can also be tested as applicable. In another embodiment, two or more pads of a die are electronically coupled together such that leakage current testing applied by a probe connected to one pad can be used to test another pad.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Abstract: An apparatus for interfacing a test head to a peripheral system is provided. The apparatus includes a first unit having a first connection member for providing electrical communication with the peripheral system, a second unit having a second connection member for providing electrical communication with the test system, and pivot members coupling the first unit and the second unit. The pivot members enable motion in the following sequence as one of the first and second unit moves towards the other: a) pivotal motion between the first connection member and the second connection member; and b) linear motion which decreases linear distance between the first connection member and the second connection member while maintaining respective contact surfaces of the first and second connection members in parallel.

Abstract: An apparatus for interfacing a test head to a peripheral system is provided. The apparatus includes a first unit having a first connection member for providing electrical communication with the peripheral system, a second unit having a second connection member for providing electrical communication with the test system, and pivot members coupling the first unit and the second unit. The pivot members enable motion in the following sequence as one of the first and second unit moves towards the other: a) pivotal motion between the first connection member and the second connection member; and b) linear motion which decreases linear distance between the first connection member and the second connection member while maintaining respective contact surfaces of the first and second connection members in parallel.

Abstract: A method and apparatus for wafer inspection. The apparatus is capable of testing a sample having a first layer that is at least partly conductive and a second, dielectric layer formed over the first layer, following production of contact openings in the second layer, the apparatus includes: (i) an electron beam source adapted to direct a high current beam of charged particles to simultaneously irradiate a large number of contact openings at multiple locations distributed over an area of the sample; (ii) a current measuring device adapted to measure a specimen current flowing through the first layer in response to irradiation of the large number of contact openings at the multiple locations; and (iii) a controller adapted to provide an indication of the at least defective hole in response to the measurement.

Abstract: The ATE system includes a system computer. A plurality of platform computers is in communication with the system computer. A plurality of test instrument boards is provided. Each of the platform computers is in communication with at least one of the test instrument boards. At least one device interface board is provided. Each of the plurality of test instrument boards is in communication with at least one of the device interface boards. At least one device mover is proximate to at least one of the device interface boards for moving devices under testing to at least one of the device interface boards.

Abstract: It is an object of the present invention to provide a double-ended contact probe that can be improved in productivity to ensure that the contact members are stably movable with respect to each other, and electrically connected to each other.

Abstract: A wafer probe station is equipped with an integrated environment control enclosure substantially surrounding a supporting surface for holding a test device, such enclosure limiting fluid communication between the interior and exterior of the enclosure and preferably also providing EMI shielding and a dark environment. The limited communication between the interior and exterior of the enclosure is kept substantially constant despite positioning movement of either the supporting surface or probes. The positioning mechanisms for the supporting surface and probes each are located at least partially outside of the enclosure.

Abstract: A method is provided for measuring interface trap density in a semiconductor device. In the method, measurement parameters are input to a host computer. A pulse condition is set at a pulse generator using the measurement parameters. A pulse of a predetermined frequency generated by the pulse generator is applied to a gate of a transistor, and a charge pumping current is measured from a bulk of the transistor. A charge pumping current measurement may be repeated for a plurality of frequencies while changing the frequency until a set frequency is reached. A pure charge pumping current is calculated for each frequency where a gate tunneling leakage current is removed from the charge pumping current measured for each frequency. Interface trap density is calculated from the calculated pure charge pumping current for each frequency.

Abstract: For an inspection of a display device which incorporates a driver circuit around pixels, a start pulse and a clock pulse are required to be inputted as inspection signals. The more complex the driver circuit is, the more complexity the start pulse and the clock pulse tend to have, which will increase the manufacturing cost of inspection signals. In addition, since a clock generator is required, cost of an inspection device is increased. Furthermore, it will lead to a longer inspection time. By setting all the power supplies for the driver circuit at a desired potential, a desired potential is outputted regardless of an input signal.

Abstract: A test head for testing electronic parts including a base having radial slots for receiving contact mounting assemblies. The contact mounting assemblies are removably mounted to the base and are radially adjustable in order to test parts having different diameters and bar counts. The contact mounting assemblies each include a piston cylinder and each removably receive a contact probe assembly carrying a plurality of spring loaded contact probes that are easily replaceable.

Abstract: A metallization pattern for a wafer translator provides a high density layout of interdigitated contact pads, suitable for component placement, along with larger contact pads suitable for connection to external equipment terminals. In another aspect, electrically conductive material may be added to, or removed from, the high density layout of interdigitated contact pads and larger contact pads to modify, or reconfigure, the electrical pathways of the wafer translator.

Abstract: An electrical contact device of a probe card includes a base and probes on the base. The base has a top side with a cavity thereon, and the cavity has sidewalls connected to the top side. Anchored portion are provided on the sidewalls of the cavity. Each of the probes has a first end and a second end, wherein the first end is connected to the anchored portion, and the second end is extended toward the cavity respectively.