Abstract: A probe station includes a fully guarded chuck assembly and connector mechanism for increasing sensitivity to low-level currents while reducing settling times. The chuck assembly includes a wafer-supporting first chuck element surrounded by a second chuck element having a lower component, skirting component and upper component each with a surface portion extending opposite the first element for guarding thereof. The connector mechanism is so connected to the second chuck element as to enable, during low-level current measurements, the potential on each component to follow that on the first chuck element as measured relative to an outer shielding enclosure surrounding each element. Leakage current from the first chuck element is thus reduced to virtually zero, hence enabling increased current sensitivity, and the reduced capacitance thus provided by the second chuck element decreases charging periods, hence reducing settling times.

Abstract: In one embodiment, the invention provides a test assembly for electrically connecting a test component to a testing machine for testing electrical circuits on the test component. The assembly comprises a contactor assembly to interconnect with the test component, a probe assembly to mechanically support the contactor assembly and electrically connect the contactor assembly to the testing machine, and a clamping mechanism comprising a first clamping member and a second clamping member, the clamping members being urged together to exert a clamping force to deform contactor bumps of an electrical connection between the probe assembly and the contactor assembly.

Abstract: The present invention provides a synchronous semiconductor device suitable for improving the efficiency of application of electrical stresses to the device, an inspection system and an inspection method thereof in order to efficiently carrying out a burn-in stress test. A command latch circuit having an access command input will output a low-level pulse in synchronism with an external clock. The pulse will pass through a NAND gate of test mode sequence circuit and a common NAND gate to output a low-level internal precharge signal, which will reset a word line activating signal from the control circuit. Simultaneously, an internal precharge signal passing through the NAND gate will be delayed by an internal timer a predetermined period of time to output through the NAND gate a low-level internal active signal, which will set a word line activating signal from the control circuit.

Abstract: A probe for an array of interconnecting leads between a PCA and an IC has one or more contacts extending laterally from or plated upon one or more arms formed of a flexible printed circuit, and connected by traces along the arm(s) to a header that itself affords connection to measurement equipment. The flexible printed circuit is thin enough to loosely slide between the top of the PCA or PCB and the bottom of the IC. The arm or arms is/are narrow enough to slide between the adjacent leads forming the array, while the normally flat contacts will successively interfere with, to engage and electrically contact, consecutive layers of leads as the probe is progressively inserted. An arm is not so stiff that it cannot yield by a slight compressive warping as the contacts encounter leads. Indexing may be ‘by feel’ or by visible indicia along a top surface of the probe or by a reticle device that moves over the top of the IC, which then has a pattern of indicia corresponding to lead location.

Abstract: A modular probe card comprises a printed circuit board, an interposer, and a probe head where the printed circuit board has a plurality of first contact pads, the probe head has a plurality of second contact pads. The interposer is disposed between the printed circuit board and the probe head where the interposer includes a substrate and a plurality of pogo pins. The substrate has a first surface, a second surface, and a plurality of through holes penetrating from the first surface to the second surface. The pogo pins are secured in the through holes of the substrate.

Abstract: A interface board is provided with a first and second contact instruments each comprising a first and second contact terminal groups to which a first to third type semiconductor devices having different numbers of external terminals used can be connected. The first contact terminal group of the first contact instrument is connected to the corresponding terminals of the second contact terminal group of the second contact instrument using bridging lines. One end of each bridging wire is connected to a driver output pin of an IO channel provided in pin electronics. The other end of the bridging wire is connected to a comparator input pin of the IO channel provided in the pin electronics. The first contact terminal group of the second contact instrument is connected, using different connection lines, to a driver output pin and a comparator input pin of an IO channel provided in the pin electronics.

Abstract: Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

Abstract: A probe card assembly has a probe contractor substrate having a plurality of probe contractor tips thereon and a probe card wiring board with an interposer disposed between the two. Support posts contacting the probe contractor substrate are vertically adjustable until secured by a locking mechanism which is coupled to the probe card wiring board. When the posts are secured in a fixed position, the position is one in which the plane of the plurality of probe contractor substrates is substantially parallel to a predetermined reference plane.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consists of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: The present invention relates to a probe for making electrical connection to a contact pad on a microelectronic device. A foot having a length, a thickness, a width, a proximal end, and a distal end, is connected to a substrate. The length of the foot is greater than its width. A torsion bar having a length, a width, a thickness, a proximal end, and a distal end, is connected to the distal end of the foot at the proximal end of torsion bar. The torsion bar lies in a first plane. A spacer having a length, a width, and a thickness, is connected to the distal end of the torsion bar. An arm having a length, a width, a thickness, a proximal end, and a distal end is connected to said spacer at the arms proximal end. The arm lies in a second plane and the second plane is in a different plane than the first plane. A first post having a top side and a bottom side is connected to the arm near the distal end of the arm. A tip is electrically connected to the top side of the post.

Abstract: A measuring method for measuring currents with a large dynamic range by means of a magnetic measuring module has the steps of switching into a high-current mode when a current threshold value is exceeded, and switching into a low-current mode otherwise, wherein the low-current mode has the following steps:—Feeding a first current pulse to a compensation coil, which drives a magnetic core in a first direction until magnetic saturation occurs,—measuring a first primary current value I1 after the current pulse is disconnected,—feeding a second current pulse to the compensation coil, which drives the magnetic core in a counter second direction until magnetic saturation occurs,—measuring a second primary current value I2 after the second current pulse is disconnected,—determining the corrected primary current value subsequently as an average value I=(I1+I2)/2 from the first and the second primary current values.

Abstract: A temperature control system, which includes a miniature liquid-cooled heat sink, is used to provide a controlled temperature surface to an electronic device, such as a semiconductor device, during the testing or burn-in phase. In one embodiment, the system includes a miniature liquid-cooled heat sink device having a monolithic counter-flowing structure. In other embodiments, the system includes a heater, a flow control valve, a controller, and/or sensors.

Abstract: A system is configured to obtain electromagnetic data from a circuit board. A set of sensing locations resides in a plane which is substantially parallel to the circuit board. The system includes a probe, a robotic assembly coupled to the probe, and a controller coupled to the probe and the robotic assembly. The controller is configured to move the probe to various sensing locations (e.g., a two-dimensional grid of sensing locations) and collect electromagnetic data from these sensing locations. The controller is further configured to provide an electromagnetic data output based on the collected electromagnetic data. The controller is further configured to direct the probe (or an adjacent probe) to emit electromagnetic interference at these locations in order to determine the effect of such interference on circuit board operation.

Abstract: This invention discloses a circuit for performing an unclamped inductive test on a metal oxide semiconductor field effect transistor (MOSFET) device driven by a gate driver. The circuit includes a current sense circuit for measuring an unclamped inductive testing (UIS) current that increases with an increase of a pulse width inputted from the gate driver to the MOSFET device wherein the current sensing circuit is provided to turn off the gate driver when a predefined UIS current is reached. The test circuit further includes a MOSFET failure detection circuit connected to a drain terminal of the MOSFET device for measuring a drain voltage change for detecting the MOSFET failure during the UIS test. The test circuit further includes a first switch for switching ON/OFF a power supply to the MOSFET device to and a second switch connected between a drain and source terminal of the MOSFET.

Abstract: A chuck for a probe station.

Abstract: A wafer probe station is equipped with an integrated environment control enclosure substantially surrounding a supporting surface for holding a test device, such enclosure limiting fluid communication between the interior and exterior of the enclosure and preferably also providing EMI shielding and a dark environment. The limited communication between the interior and exterior of the enclosure is kept substantially constant despite positioning movement of either the supporting surface or probes. The positioning mechanisms for the supporting surface and probes each are located at least partially outside of the enclosure.

Abstract: An electro-optical device includes a first substrate that holds an electro-optical material, a first IC that is mounted on the first substrate and that has a plurality of first terminals, a plurality of second terminals that are formed on the first substrate to be connected to the plurality of first terminals, respectively, a plurality of wiring lines formed on the first substrate, first connection state diagnostic terminals that are included in the plurality of first terminals and that are used for diagnosing connection states between the first terminals and the second terminals, second connection state diagnostic terminals that are included in the plurality of second terminals and that are connected to the first connection state diagnostic terminals, respectively, a connection state diagnostic unit that is provided in the first IC to diagnose whether the first and second connection state diagnostic terminals are electrically connected to each other, and a connection state diagnosis result output unit that i

Abstract: The present application relates to apparatus and methods for burn-in and other diagnostics performed on integrated circuits. In one embodiment, the invention includes a plurality of sockets, each to hold an integrated circuit (IC), and coupling power to the respective IC from a remote power supply, a plurality of voltage detectors, each coupled to a socket to sense the voltage of the power coupled to the respective IC, and a plurality of remote voltage regulators, each coupled between the power supply and a respective socket, to receive the sensed voltage from the respective voltage detector and to adjust the voltage of the respective coupled power in accordance therewith.

Abstract: A test apparatus for integrated circuits includes a data collector (1). The data collector includes a cantilever (10) and at least one probe (20). The probe is formed at a free end (18) of the cantilever and includes at least one carbon nanotube (22). A method for manufacturing the test apparatus for integrated circuits includes the steps of: (a) forming a substrate (12) at a free end of a cantilever; (b) forming at least one electrically conductive film (14) on the substrate; (c) depositing at least one catalyst film (16) on the corresponding electrically conductive film; and (d) depositing at least one carbon nanotube on each catalyst film thereby forming at least one probe thereat.

Abstract: The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of locations on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.