Abstract: A probe apparatus includes a nest element operable to precisely locate a chip having a plurality of exposed interconnects on a face of the chip to permit conductive connection to the chip through the interconnects. The nest element includes a pocket dimensioned to locate the chip within a tolerance of less than a width of one of the interconnects, and tapered walls extending upwardly and outwardly from the pocket, the tapered walls adapted to guide the chip into the pocket. One or more piezoelectric elements can be attached to or provided within to the nest element to impart vibration to the nest element, causing the chip to be “fluidized” such that the chip is guided into the pocket under the force of gravity or other externally applied force.

Abstract: An adjusting device for a chip adapter. The adjusting device comprises a main body having a plurality of adjusting holes into which testing pins of the adapter are inserted and a slider disposed on the main body and sliding perpendicular to the top surface thereof for easy removal the chip adapter without mis-alignment of testing pins.

Abstract: An electronic test system load board electromagnetic shield is presented. The load board electromagnetic shield may have a DUT docking plate having a periphery rim on a first side with an aperture extending through the docking plate that has a waveguide chimney through which a DUT may be inserted into a socket or contactor on the load board.

Abstract: The object of the present invention is to provide an inspection apparatus for liquid crystal drive substrates that improves the inspection accuracy of liquid crystal drive substrates, judges defect type more accurately, and does not cause a decrease in throughput.

Abstract: The invention relates to a method for analysing connection conditions between an integrated circuit package and a circuit board, wherein said integrated circuit package is electrically coupled to said circuit board by coupling elements, and therein said integrated circuit package is mechanically connected with said circuit board by support elements. To allow easy failure analysis, it is proposed that physical values are picked-off from said support elements, and said physical values are evaluated to determine the condition of said connection between said integrated circuit package and said circuit board.

Abstract: Apparatus and methods are provided for measuring the potential for mutual coupling in an integrated circuit package of any type or configuration using a network analyzer in conjunction with a coaxial test probe. Simple, low-cost test fixturing and methods of testing may be used to measure the parasitic capacitance and inductance of one or more I/O leads of an integrated circuit package, the measured parasitic capacitances and inductances providing an indication of the susceptibility of the integrated circuit package to mutual coupling between electrical leads of the package or between an electrical lead and other components of the integrated circuit package.

Abstract: A testing apparatus, system and method for testing computer memory modules are disclosed. The apparatus includes a motherboard having a processor and at least one resident memory socket fixed to the motherboard. A remote memory socket is provided and located a distance from the resident memory socket, such as on a periphery of the motherboard. The remote memory socket is coupled to the resident memory socket by a conductor assembly such as a ribbon cable and an adapter. A memory module is placed in the remote memory socket and tested using a signal or combination of signals from the processor. A plurality of motherboards, each being configured with remote memory sockets, may be combined to form a testing system suitable for use with an automated handler.

Abstract: An interconnection contact structure assembly including an electronic component having a surface and a conductive contact carried by the electronic component and accessible at the surface. The contact structure includes an internal flexible elongate member having first and second ends and with the first end forming a first intimate bond to the surface of said conductive contact terminal without the use of a separate bonding material. An electrically conductive shell is provided and is formed of at least one layer of a conductive material enveloping the elongate member and forming a second intimate bond with at least a portion of the conductive contact terminal immediately adjacent the first intimate bond.

Abstract: A method and apparatus for a thermal stratification test providing cyclical and steady-state stratified environments. In order to test an electronic device, for example one having one or more levels of ball-grid-array interconnections, e.g., connecting a chip to a flip-chip substrate and connecting the flip-chip substrate to a printed circuit board of a device, an apparatus and method are provided to heat one side of the device while cooling the second side. In some embodiments, the process is then reversed to cool the first side and heat the second. Some embodiments repeat the cycle of heat-cool-heat-cool several times, and then perform functional tests of the electronic circuitry. In some embodiments, the functional tests are performed in one or more thermal-stratification configurations after cycling at more extreme thermal stratification setups. In some embodiments, a test that emphasizes solder creep is employed.

Abstract: Output data of a device under test (DUT) is obtained at timing of both rising and falling edges of a clock output from the DUT, and output data of a DDR type device is fetched in synchronization with the clock. A semiconductor test apparatus comprises a clock side time interpolator 20 which obtains clocks input from a DUT 1 by a plurality of strobes of constant timing intervals and which outputs the clocks as time-sequential level data, a data side time interpolator 20 which obtains output data input from the DUT 1 by a plurality of strobes of constant timing intervals and which outputs the output data as time-sequential level data, and an edge selector 30 which switches the time-sequential level data obtained by the time interpolators 20 and selectively outputs level data indicating rising and/or falling edges of the level data.

Abstract: An anisotropically conductive connector, inhibits permanent deformation by contact of target electrodes to be connected with pressure and deformation by abrasion from occurring even if the target electrodes to be connected are those projected, achieves stable conductivity over a long period of time even when it is pressed repeatedly, and prevents or inhibits an object of connection from adhering, a production process thereof, and an inspection apparatus for circuit devices equipped with the anisotropically conductive connector. The anisotropically having an anisotropically conductive film, in which a plurality of conductive path-forming parts each extending in a thickness-wise direction of the film are arranged in a state mutually insulated by insulating parts.

Abstract: A device includes a magnetic-field sensor and an ammeter, in which a field distribution of a first electric field is provided in a region so that the magnitude of the x component of the first electric field increases in the x direction.

Abstract: A method of modifying a semiconductor device to provide electrical parameter monitoring. The device includes a semiconductor die and a package substrate. The substrate includes a conductive plane. The die is connected to the plane via a plurality of connection structures. The method includes disconnecting a first one of the connection structures from the plane, and connecting the first connection structure to an external package connection, thereby providing a capability to monitor an electrical parameter of the die via the external package connection.

Abstract: A method and system for probing with electrical test signals on an integrated circuit specimen using a high resolution microscope positioned for observing a surface of the specimen exposing electrically conductive terminals thereon. A housing is provided with a carrier therein for supporting the specimen in relation to the microscope and a probe assembly is positionable on the surface of the specimen for conveying and acquiring electrical test signals to and from the specimen. A drive system is provided for shifting at least one of the probe and the carrier to a predetermined test position. In one form the system has a heat shield for protecting one of the probe assembly and the carrier from heat energy generated upon operation of the drive system, and in another form, the system has an environmental control for maintaining a desired temperature within the housing so that accurate measurements may be taken from the specimen.

Abstract: An integrated printed circuit board and test contactor for high speed semiconductor testing having an alignment housing with a cavity for receipt and positioning of the integrated circuit to be tested, a printed circuit board having a non-conductive elastomer portion positioned along a surface of the printed circuit board and an electrically balanced microwave transmission line structure having flexible fingers for transmitting test signals from the integrated circuit through the printed circuit board. A U-shaped ground element extends around the microwave transmission line structure.

Abstract: One embodiment of the present invention is a method for fabricating a structure useful for testing circuits that includes steps of: (a) aligning a first side of a connector-holder comprised of electrical connectors having retractable ends that are extendable out of the first side of the connector-holder and having retractable ends that are extendable out of a second side of the connector-holder with a substrate; and (b) connecting ends extendable out of the first side to pads on the substrate to form the structure.

Abstract: A Time Dependent Dielectric Breakdown (TDDB) test pattern circuit, which can reduce testing time and statistically improve a precision of measurement as well as a method for testing the test pattern circuit are discussed. Typically, a test pattern circuit includes in plurality of unit test patterns. Each unit test pattern includes a capacitor connected to a stress voltage. The stress voltage is applied to the capacitor and the current flowing from the capacitor is measured over time. The dielectric in the capacitor breaks down over time and at a certain point, the current from the capacitor changes suddenly. Unfortunately, the convention test pattern circuit requires serial testing of each unit cell, and therefore, the measuring time is significant when there are many unit cells involved. The circuit allows for the measurements to take place simultaneously for all unit cells within the test pattern circuit.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

Abstract: An IC socket suction cap and an IC socket assembly that employs the suction cap are configured to reduce the risk of deforming a housing of the IC socket assembly. The IC socket assembly includes a loading plate for applying pressure on the IC socket housing by the operation of a lever. The IC socket suction cap includes a flat suction surface, latch arms for latching and engaging the housing, and loading plate holding pieces, for holding the loading plate in a state in which it does not exert pressure onto the housing.

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.