Abstract: A semiconductor memory card (101) has a plurality of areas (105, 106) based on different file systems. An adapter (102) includes: an area switching part (110) which a user can operates, a determination part (109) for determining the operation; and a card controller (108) for issuing a switching command for switching the area to be used for the semiconductor memory card (101) in accordance with the judgment result. When the switching command is issued in response to input from the area switching part (110), the command is interpreted by an area selector (107) of the semiconductor memory card (101) so as to select an area.

Abstract: Disclosed are a system, a method and device for recognizing an external device by a portable terminal. The external device determines whether the external device has recognized the portable terminal according to signals with a predetermined form, which have been output from the portable terminal regardless of the on/off state of the power source thereof, and outputs signals for a predetermined period of time according to a result of the determination. Thereafter, the portable terminal recognizes the external device according to the number or the form of signals input from the external device through a recognition node for a predetermined period of time. As a result, the portable terminal can recognize more various external devices, such as an external battery and a charging cradle which provides stereo sound, by using the recognition node of the portable terminal.

Abstract: In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.

Abstract: An I/O module expansion unit having slots to install I/O modules thereon is provided for a distributed automation system. With the I/O module expansion unit, storing the configuration checksums generated with an algorithm from the software and hardware information of I/O modules, the distributed automation system can simplify the identification of an I/O module. By directly writing the configuration parameters stored in the I/O module expansion unit into the installed I/O module, the distributed automation system can simplify the setting and replacement of an I/O module. The I/O module expansion unit may also fast detect a hot-swap of an I/O module by wiring to the slots.

Abstract: The present invention relates to a computer system and a monitor with peripheral interfaces. The computer system includes a monitor, a host, and a transmission cable. The monitor includes a plurality of peripheral interfaces and an integrated interface. The peripheral interfaces are utilized to connect corresponding peripheral devices, and the peripheral interfaces are connected with the integrated interface. The transmission cable is configured for connecting the integrated interface and the host, and transmitting peripheral signals from the peripheral devices to the host.

Abstract: An integrated circuit includes a plurality of tiles. Each tile comprises a processor; a switch including switching circuitry to forward data over data paths from other tiles to the processor and to switches of other tiles; a receive buffer to store the data received by the switch; and a sorting module to provide data to the processor from the receive buffer, the sorting module comprising one or more buffers that are each configured to store data from the receive buffer based on a tag in the data.

Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

Abstract: A storage system filter provides protocol aware filter operations that avoid I/O blocking or calling thread holding. A filter framework includes a filter controller that handles request and response calls to filters that are registered with the filter framework. Filters may be loaded and unloaded in a consistent state, and the filter framework provides services for the filters for common functions. Filters may operate in a user mode or a kernel mode and may be invoked in a synchronous, an asynchronous, or an asynchronous release mode. Filter registration may include registration for I/O resources, and may include tagging of I/O requests and responses to contribute to preventing conflicts.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.

Abstract: An information processing apparatus may include plural media capable of recording data, and a control unit executing operation control of the plural media and at least one medium in the plural media may be a mechanical operation executing medium performing mechanical operations, and the control unit may decide whether the mechanical operation executing medium is selected as an access target, and when the medium is not selected as the access target, perform processing of setting the mechanical operation executing medium to a waiting state.

Abstract: Techniques are disclosed to provide generic USB drivers. More particularly, a generic USB device driver architecture is described which enables development through a user-mode USB library that accesses a generic kernel-mode driver. In a described implementation, a method includes loading a kernel-mode generic device driver in response to a plug-in event of a device. A user software component accesses the device by utilizing routines provided by the generic user-mode library (e.g., a dynamic link library (DLL)) that communicates with the generic device driver.

Abstract: A dummy node is enqueued to a concurrent, non-blocking, lock-free FIFO queue only when necessary to prevent the queue from becoming empty. The dummy node is only enqueued during a dequeue operation and only when the queue contains a single user node during the dequeue operation. This reduces overhead relative to conventional mechanisms that always keep a dummy node in the queue. User nodes are enqueued directly to the queue and can be immediately dequeued on-demand by any thread. Preferably, the enqueueing and dequeueing operations include the use of load-linked/store conditional (LL/SC) synchronization primitives. This solves the ABA problem without requiring the use a unique number, such as a queue-specific number, and contrasts with conventional mechanisms that include the use of compare-and-swap (CAS) synchronization primitives and address the ABA problem through the use of a unique number.

Abstract: The process acquires data blocks in real-time with a fast scanner. The acquired data blocks are then transmitted to a computer system (23). The data blocks are then processed as a function of a frame burst ratio (N). The transmission of the acquired data blocks to the computer system is a function of the frame burst ratio (N). The frame burst ratio (N) may be either fixed or variable. In any case, optimal utilization of the computer system's (23) performance is important. The frame burst ratio (N) is selected by the user or by the computer system (23) itself as a function of the processing characteristics of the computer system (23).

Abstract: A method and apparatus to read information from an information storage medium using a read channel, where that read channel includes a data cache. The invention generates an analog waveform comprising the information, and provides that analog waveform to a read channel, and generates a digital signal from that analog waveform using one or more first operating parameters. The method error corrects that digital signal at an actual error correction rate, and determines if the actual error correction rate is greater than an error correction rate threshold. If the actual error correction rate exceeds the error correction rate threshold, then the method captures the digital signal, stores that captured data in a data cache, reads that digital signal from the cache, generates one or more second operating parameters, and provides those one or more second operating parameters to the read channel.

Abstract: The invention is provided to improve the information processing efficiency of a multiprocessor system. An information processing apparatus 1000 comprises a main processor 200 for exercising centralized control on the entire apparatus, a graphic processor 100 for performing image processing operations, and a main memory 50. The information processing apparatus 1000 also comprises a DMA controller 28 which controls m (m is an integer, m>1) pieces of data transfer simultaneously, a main memory 50 for data intended for the particular processing is expanded first, and a group of n (n is an integer, n>m) buffers 12 for storing data when the data is transferred from the main memory 50. When a plurality of data transfers are performed simultaneously, a first buffer out of the group of buffers 12 is set as the destination of one of the data transfers, and a second buffer is set as the destination of another data transfer.

Abstract: The present invention relates to a method of implementing an internal memory of a computer peripheral device as an optical storage device or/and a removable disk by software emulation. The computer peripheral device does not include additional hardware for driving the computer peripheral device as an optical storage device or/and a removable disk. A part of the internal memory of the computer peripheral device functions as a virtual optical storage device or/and a removable disk through software emulation. To achieve this, an emulation program is added to the computer peripheral device. The internal memory stores a program for recognizing the operating system and hardware type of a host as well as a device utilization application.

Abstract: A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.

Abstract: The disclosure relates to a method for configuring field devices in a process automation system wherein the field devices are connected to other automation components by means of a field bus. In order to minimize the load placed on the field bus, a copy of the current configuration of each field device is stored in a configuration tool, the appropriate set of configuration and parameter data is transmitted to each field device during initial start-up and modifications in relation to the previous copy of the configuration and parameter data are transmitted to the respective field device.

Abstract: Embodiments of the invention relate to methods and systems for providing customized “haptic messaging” to users of handheld communication devices in a variety of applications. In one embodiment, businesses and organizations may each be associated with a distinct haptic logo and include their haptic logos in various messages sent to the handheld communication devices of their customers. In another embodiment, haptically-enabled avatars can be used in a chat session between users of handheld communication devices.

Abstract: A peripheral device is disclosed having two associated memory modules, and which is configured to fit within the ExpressCard slot. One memory module communicates with a host over the PCIe bus interface of the ExpressCard slot, while the other memory module communicates with the host over the USB interface of the ExpressCard slot.