Abstract: A multi-port SERDES transceiver includes multiple parallel and serial ports, and the flexibility to connect any one of the parallel or serial ports to another parallel or serial port. The ports include programmable pads that are capable of supporting multiple different data protocols, timing protocols, electrical specifications, and input-output functions. A management data IO pad also enables the transceiver to support different electrical requirements and data protocols at the same time. The substrate layout of the transceiver is configured so that the parallel ports and the serial ports are on the outer perimeter. A logic core is at the center, where the logic core operates the serial and parallel data ports, and the bus that connects the data ports. The bus can be described as a “ring” structure (or donut “structure”) around the logic core, and is configured between the logic core and the data ports.

Abstract: An information processing apparatus includes a communication processing unit configured to communicate with an external communication device; and a data processing unit configured to communicate with the communication processing unit and carry out data processing. The communication processing unit includes a memory where data transmitted and received between a communication device and the data processing unit is temporarily stored, and a control unit configured to control data writing and data reading. When a command packet received from the communication device is a data reading request, the control unit acquires data from the memory and transmits the data to the communication device. When the command packet received from the communication device is a data writing request, the control unit stores data in the memory, acquires data from the memory in response to the request from the data processing unit, and outputs the data to the data processing unit.

Abstract: Memory devices having a memory module, an interface, identification circuitry and a controller coupled to the memory module and the identification circuitry. The identification circuitry is configured to identify a selected operating mode from a plurality of signals sensed at the interface in response to a plurality of signals previously applied to the interface by the identification circuitry. The controller is operable to configure the memory device to the selected operating mode responsive to the identification circuitry.

Abstract: A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.

Abstract: A system controller is presented that controls an output format of data according to a data congestion status of the data and then outputs the data over an output bus. Specifically, if there is data congestion, the system controller changes the format of the data to a format that matches a bus width of the output bus before outputting the data over the output bus. To give a specific example, the system controller changes the format of the data input over an input bus in an input format of 4 B to an output format of 5 B before outputting the data over the output bus. If there is no data congestion, the system controller outputs the data over the output bus without changing the input format.

Abstract: A data backup system is provided that when coupled to a data source, such as a personal computer, and a media player, such an Apple Computer IPod media player, the data backup system blocks certain communications between the data source and the media player thus preventing the data source from recognizing the media player as such thereby avoiding the launching of synchronization software for the media player, the data backup system also causing the automatic launching of a backup application stored on the data backup system so that data files can be located on the data source and then backed up to the media player.

Abstract: Method of processing data of at lease one data stream, data processing module for processing at a of at least one data stream, data processing system comprising such module, computer program product, data storage system and method of use thereof. For a time-based transfer of data to or from a device, data streams may be given a system ID and it is proposed to dynamically distribute available stream IDs. The proposed concept provides for indicating a type of data stream, providing and/or handling a set of stream IDs comprising a number of stream IDs and issuing a stream ID from the set of stream IDs to the data stream depending on the type of data stream. In a preferred embodiment, it is proposed to reserve one stream ID for an audio-video request, characterized by having no error handling time available. A further stream ID may be reserved for best effort requests.

Abstract: A method for arbitrating between a host device and a cellular base band mode for use of a shared SD storage, including requesting, by a cellular base band modem from a host device, access to an SD storage, including writing an access request message, notifying the host device of the access request message, reading, by the host device, the access request message, granting, by the host device, the access request, including writing an access grant message, notifying the cellular base band modem of the access grant message, reading, by the cellular base band mode, the access grant message, holding an SD host bus in a busy state, thereby forcing the host device to hold and not access the bus, accessing, by the cellular base band modem, the SD storage, and upon completion of the accessing, removing the busy state from the SD host bus.

Abstract: A system and method for online configuration of a measurement system. The user may access a server over a network and specify a desired task, e.g., a measurement task, and receive programs and/or configuration information which are usable to configure the user's measurement system hardware (and/or software) to perform the desired task. Additionally, if the user does not have the hardware required to perform the task, the required hardware may be sent to the user, along with programs and/or configuration information. The hardware may be reconfigurable hardware, such as an FPGA or a processor/memory based device. In one embodiment, the required hardware may be pre-configured to perform the task before being sent to the user. In another embodiment, the system and method may provide a graphical program in response to receiving the user's task specification, where the graphical program may be usable by the measurement system to perform the task.

Abstract: Method and system for latency-independent peripheral device identification. The computer system receives an interrupt from a peripheral device via a communications port. In response, an interrupt notification message is posted to alert a notification handler, and compliant peripheral class is determined. The voltage on a device may sense pin of the communications port for this determination. If the interrupt is indicative of the compliant peripheral class and the communications port is inactive, the port is opened, and an inquiry is sent and a response is received. If a response is received within a predetermined time period, an identification notification message is posted based on the response including information for classifying the peripheral device, so that a software handler registered with the operating system can handle the identification notification message when the software handler receives it. Thus, no time-critical interrupt response requirement is imposed for its successful operation.

Abstract: A memory card capable of connecting to a host device includes a flash memory, a host interface unit which transfers data between a host device and the memory card, and a transfer mode control unit which changes a data transfer mode based on a command from the host device. The transfer mode control unit outputs status data containing an error code to the host device if a transfer mode change command is inputted from the host device, instructing the memory card to change to a transfer mode not supported by the host interface unit of the memory card.

Abstract: A floppy module includes a floppy disk controller (FDC), a control circuit, and a display. The FDC has a first control terminal, a second control terminal, and a plurality of third control terminals. Wherein, the first control terminal and the second control terminal may respectively output a first control signal and a second control signal, and the first and second control signals having the same statuses are used for controlling a floppy disk. The display has a fourth control terminal and a plurality of data terminals respectively coupled to a portion of the third control terminals. Additionally, the control circuit may use the first control signal to replace the second control signal for controlling the floppy disk, and transmit the second control signal to the fourth control terminal such that a status information is shown on the display as the floppy disk being idle.

Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.

Abstract: A system and method are provided for accelerating data transfer between networked databases. First provided are a plurality of databases coupled by a network. At least one laser unit is coupled to each database. In operation, such laser units are capable of communicating data between the databases via free space by way of a laser beam. This allows data communication at a rate faster than that which the network is capable.

Abstract: A method is provided for generating a control vector. The method comprising: providing a circular buffer having a plurality of storage elements that are arranged sequentially from a designated first storage element to a designated last storage element, and when the designated last storage element of the plurality of storage elements is accessed, the access continuing in a sequential order continuing with the designated first storage element; determining a beginning storage element of the plurality of storage elements to be accessed; and generating a control vector, the control vector comprising a plurality of index values, each of the plurality of index values corresponding to one of the plurality of storage elements of the circular buffer to be accessed in the sequential order from the beginning storage element to an ending storage element.

Abstract: An apparatus and method is disclosed for providing an extensible information handling system (IHS) bus implemented on predetermined channels of a digital video interface. IHS video signal information is multiplexed with IHS bus information by a host multiplexer for transmission across a digital video connector. The multiplexed IHS video signal and IHS bus information is received by a display multiplexer, where it is demultiplexed. Demultiplexed IHS video signal information is received by a video interface receiver, where it is used to generate an image on a digital display. Demultiplexed IHS bus information is received by a host bus interface transmitter/receiver, where it is used to support peripheral devices attached to the digital display.

Abstract: In an embodiment, buffer constructs may be generated to be associated with any one of multiple mutually exclusive states, including an open state and a closed state. When the buffer construct is in the closed state, the region of memory represented by the buffer construct is made accessible to one or more direct memory access (DMA) operations. Upon completion of the one or more DMA operations, the buffer construct transitions from the closed state to the open state. The region of memory represented by the buffer construct is made accessible for use with one or more cache operations when the buffer construct is in the open state, so that the one or more cache operations are not in conflict with the one or more DMA operations.

Abstract: Systems and methods for commonality factoring for storing data on removable storage media are described. The systems and methods allow for highly compressed data, e.g., data compressed using archiving or backup methods including de-duplication, to be stored in an efficient manner on portable memory devices such as removable storage cartridges. The methods include breaking data, e.g., data files for backup, into unique chunks and calculating identifiers, e.g., hash identifiers, based on the unique chunks. Redundant chunks can be identified by calculating identifiers and comparing identifiers of other chunks to the identifiers of unique chunks previously calculated. When a redundant chunk is identified, a reference to the existing unique chunk is generated such that the chunk can be reconstituted in relation to other chunks in order to recreate the original data. The method further includes storing one or more of the unique chunks, the identifiers and/or the references on the removable storage medium.

Abstract: The present invention provides a computer, comprising: a processor for processing data; a system bus connected to the processor; a management unit connected to the system bus; and an external storage connected to the system bus through the management unit, wherein the external storage comprises: a buffer for buffering data; and storage areas connected to the buffer for storing data, and wherein the management unit is adapted to: receive an instruction sent by the processor from the system bus, said instruction corresponding to operations; read data information from the storage areas to the buffer; and execute at least one of the operations on the data information. Furthermore, the present invention provides an external storage and a method for processing data information in an external storage. According to the present invention, it is possible to scan the external storage with a large capacity in a short time.

Abstract: The present invention provides an integrated circuit chip which includes a processor; a contact pad unit connected to a host through a plurality of contact pads; a host interface detector including at least one pull-up resistor and one pull-down resistor, for selectively connecting the pull-up resistor and the pull-down resistor to the contact pad unit to detect a host interface status; and an interface unit including a plurality of interface protocols, for communicating with the host using a part or all of the plurality of contact pads, wherein the processor receives a status of the host from the host interface detector, identifies a protocol of the host based on the received status of the host, and controls the interface unit so as to enable an interface protocol that is used to communicate with the host.