Abstract: A hand-held test meter for use with an analytical test strip configured for the determination of an analyte in a bodily fluid sample includes a USB interface, a microcontroller block configured for boot strap loading (BSL) of data into the hand-held test meter via a serial signal and a circuit disruption avoidance block. The circuit disruption avoidance block includes a USB to serial bridge sub-block with (i) a USB input(s), (ii) a serial output(s) configured to provide a serial signal for BSL of data to the microcontroller block; and (iii) a plurality of general purpose input/outputs (GPIO). The circuit disruption avoidance block also includes a BSL enable gate/buffer sub-block. At least two of the GPIO are configured to provide BSL control signals to the microcontroller block via the BSL enable gate/buffer sub-block and the USB to serial bridge sub-block is configured to send the data to the microcontroller block via the at least one serial output.

Abstract: Methods, controllers for data storage, data storage systems, and computer program products are directed to migrating data after the initial placement of the data in data storage entities having higher speed and in other data storage. Steps of a method to migrate data to the higher speed data storage are (1) identifying at least one group of data having had at least one I/O activity in each of a plurality of intervals of time, occurring over a string of multiple intervals of time, wherein the I/O activity is with respect to the other data storage from which data is to be migrated. The time for each of the multiple intervals is selected such that bursts of the I/O activity are likely to be contained in one interval. (2) The identified group of data is classified to the higher speed data storage and migrated.

Abstract: A hardware automated IO path, comprising a message transport unit for transporting an IO request to a local memory via a DMA operation and determining a LMID for associating with a request descriptor of the IO request; a fastpath engine for validating the request descriptor and creating a fastpath descriptor based on the request descriptor; a data access module for performing an IO operation based on the fastpath descriptor and posting a completion message into the fastpath completion queue upon a successful completion of the IO operation. The fastpath engine is further configured for: receiving the completion message, releasing the IO request stored in the local memory, and providing a reply message based on the completion message. The message transport unit is further configured for providing the reply message in response to the IO request.

Abstract: A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

Abstract: Methods and apparatus to odd and even frame combination data path architectures are described. In one embodiment, a logic may include a buffer and a parallel input, serial output (PISO) logic that may be utilized for transferring data between a source and a destination. The logic may be utilized for transferring the data whether or not the data is transmitted in accordance with single ended or differential signals. Other embodiments are also described.

Abstract: An image display device that controls an external device and a method therefore are provided. The image display device includes an interface unit which is connected to an external device, a determining unit which determines whether another external device that has a control ownership of the external device exists, and a control unit which registers the control ownership of the external device if it is determined that the other external device does not exist. The external device is controlled by registering the control ownership.

Abstract: In one embodiment of the invention, a method for data redundancy across three or more storage devices is disclosed. The method includes storing a collection of data chunks as a plurality of N-1 data stripes across N storage devices where N is three or more, wherein each data chunk of up to N data chunks forming a data stripe is stored in a different storage device; storing a parity stripe across the N storage devices including N-1 data parity chunks and one meta data parity chunk; wherein each Kth storage device of N-1 storage devices stores a Kth data parity chunk of the N-1 data parity chunks computed as parity of up to N data chunks forming the Kth data stripe; and wherein an Nth storage device of the N storage devices stores the meta parity chunk computed as parity of the N-1 data parity chunks stored in the respective N-1 storage devices.

Abstract: Disclosed herein are techniques to execute tasks with a computing device. A first task is initiated to perform an operation of the first task. A buffer construct that represents a region of memory accessible to the operation of the first task is created. A second task is initiated to perform of an operation of the second task that is configured to be timed to initiate in response to the buffer construct being communicated to the second task from the first task.

Abstract: A port setting method of an application system comprises: requesting a naming server for object information corresponding to name information of the other components upon data transmission to the other components; determining whether there exists consistent information based on the object information of the other components received from the naming server; if there exists consistent information, selecting a first and certain protocol, and otherwise, selecting a second protocol; and establishing a connection with the other components by use of the selected protocol. The actual location of the components can be sensed based on Endpoint information of IOR without adding no particular information to the domain profile (xml profile), and a more efficient protocol can be selected depending on the position of each component, thereby enhancing data transmission performance and efficiency in SCA port communications between components.

Abstract: A system, method and computer program product are provided for supporting Transactional Memory communications. In one embodiment, the system comprises a transactional memory host with a host transactional memory buffer, an endpoint device, a transactional memory buffer associated with the endpoint device, and a communication path connecting the endpoint device and host. Input/Output transactions associated with the endpoint device executed in transactional memory on the host are stored in both the host transactional memory buffer and the transactional memory buffer associated with the endpoint device. In an embodiment, the Transactional Memory system further comprises an intermediate device located on the communication path between the host and the endpoint device, and an intermediate transactional memory buffer associated with said intermediate devices.

Abstract: Mode switching may be provided. A selection of a non-native mode for a first input device may be received having a native mode. Then the use of the first input device may be enabled in the selected non-native mode. Next, a switch may be detected from the first input device to a second input device and then a switch back to the first input device may be detected. The use of the first input device may be enabled in the native mode in response to detecting the switch back to the first input device.

Abstract: A memory hub for a memory module having a DMA engine for performing DMA operations in system memory. The memory hub includes a link interface for receiving memory requests for access at least one of the memory devices of the system memory, and further including a memory device interface for coupling to the memory devices, the memory device interface coupling memory requests to the memory devices for access to at least one of the memory devices. A switch for selectively coupling the link interface and the memory device interface is further included in the memory hub. Additionally, a direct memory access (DMA) engine is coupled through the switch to the memory device interface to generate memory requests for access to at least one of the memory devices to perform DMA operations.

Abstract: A system and method for identifying lost/stale peripheral hardware devices connected to an enterprise computer system is disclosed. In one embodiment, a method for identifying lost peripheral hardware devices connected to an enterprise computer system includes initializing system memory by obtaining data structures associated with last detected connected peripheral hardware devices stored in an external database upon reboot, initiating an enterprise computer system wide scanning to obtain the detected data structures associated with current connected peripheral hardware devices during the reboot, and comparing the obtained data structures associated with the last detected connected peripheral hardware devices and the current connected peripheral hardware devices to determine whether there is any chance in system resources associated with the connected peripheral hardware devices during the reboot.

Abstract: A remote console unit includes a signal processing apparatus that receives an image signal from a computer main body and also sends and receives various signals other than the image signal to and from the computer main body through a cable for general purpose. Data input and/or output can be performed remotely to and from the computer main body through the cable.

Abstract: Certain exemplary embodiments can provide a system, which can comprise a programmable logic controller (PLC). The system can comprise a serial communications port connected to the PLC. In certain exemplary embodiments, the system can comprise a controller adapted to enable a customer application program to access and control the serial communications port.

Abstract: A system and method for transmitting asynchronous data bursts over a constant data rate channel that transmits a continuous stream of data with virtually no load on the CPU(s) of the receiving processing node is disclosed. The data channel has a defined frame structure with one or more data structures, wherein each data structure comprises a plurality of data locations. A receiver selects data from a fixed data location in each data structure as a data descriptor for each respective data structure. The receiver configures a direct memory access (DMA) function using each data descriptor.

Abstract: A storage system constituted such that power saving to an administrator-desired storage device can be performed from a management device. That is, the storage system comprises a power-saving indication receiving section for receiving from a management console a power-saving indication specifying at least one storage device of a plurality of RAID groups, a plurality of logical units, and a plurality of physical storage devices; and a power-saving controller for saving on power to one or more physical storage devices corresponding to the storage device specified in this power-saving indication.

Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

Abstract: A method for automatic learning of software keyboard input characteristics includes the following steps. (a) An input is received. (b) Whether the input is a normal key input is determined. (c) The input value of the input is stored when the input is determined to be the normal key input. (d) Step (a)-(c) are repeated until (N+1) input values are stored, wherein N is a positive integer. (e) When there are (N+1) inputs stored, the input characteristics of the first input in the (N+1) inputs are determined according to the first stored input value in the stored (N+1) input values. A computer program product using the method and a system for automatic learning of software keyboard input characteristics are also disclosed herein.

Abstract: A memory card capable of connecting to a host device includes a flash memory, a host interface unit which transfers data between a host device and the memory card, and a transfer mode control unit which changes a data transfer mode based on a command from the host device. The transfer mode control unit outputs status data containing an error code to the host device if a transfer mode change command is inputted from the host device, instructing the memory card to change to a transfer mode not supported by the host interface unit of the memory card.