Abstract: An optoelectronic module includes an optical filter and can have a relatively small overall height. The module includes a semiconductor die for the optical filter, where the die has a cavity in its underside. The cavity provides space to accommodate an optoelectronic device such as a light sensor or light emitter. Such an arrangement can reduce the overall height of the module, thereby facilitating its integration into a host device in which space is at a premium.

Abstract: A semiconductor package includes a package substrate. An interposer is disposed on the package substrate. The interposer includes a semiconductor substrate, a wiring layer disposed on an upper surface of the semiconductor substrate and having a plurality of wirings therein, redistribution wiring pads disposed on the wiring layer and electrically connected to the wirings, bonding pads disposed on the redistribution wiring pads, and an insulation layer pattern disposed on the wiring layer and exposing at least a portion of the bonding pad, and first and second semiconductor devices disposed on the interposer. The first and second semiconductor devices are spaced apart from each other and are electrically connected to each other by at least one of the wirings.

Abstract: A semiconductor package structure includes a substrate, a bridge structure, a redistribution layer, a first semiconductor component, and a second semiconductor component. The substrate has a wiring structure. The bridge structure is over the substrate. The redistribution layer is over the bridge structure. The first semiconductor component and the second semiconductor component are over the redistribution layer, wherein the first semiconductor component is electrically coupled to the second semiconductor component through the redistribution layer and the bridge structure.

Abstract: A radio frequency front-end module, a manufacturing method thereof and a communication device are provided. The radio frequency front-end module includes a first base substrate and a metal bonding structure; a second functional substrate, including a second base substrate, a groove in the second base substrate, and a bonding metal layer; and a first radio frequency front-end component, at least partially located in the groove, the first base substrate and the second base substrate are oppositely arranged, and a surface of the second base substrate close to the first base substrate includes a groove surface inside the groove and a substrate surface outside the groove, and the bonding metal layer includes a first metal portion located on the groove surface and a second metal portion located on the substrate surface, the first radio frequency front-end component is at least partially surrounded by the first metal portion.

Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).

Abstract: A semiconductor package includes a substrate, first and second semiconductor chip structures on the substrate and spaced apart from each other in a first horizontal direction, a mold layer on the substrate and covering both the first and second semiconductor chip structures, and a supporting structure on the mold layer and distal from the upper surface of the substrate than both the first and second semiconductor chip structures in a vertical direction. The supporting structure includes first and second supporting portions, spaced apart from each other in a second horizontal direction that is perpendicular to the first horizontal direction and the vertical direction. Each of the first and second supporting portions has a bar shape or a linear shape extending in the first horizontal direction. At least one of the first supporting portion or the second supporting portion overlaps the first and second semiconductor chips in the vertical direction.

Abstract: A method of manufacturing a magnetic tunnel junction (MTJ) device, including steps of forming a dielectric layer comprising a metal line therein on a substrate, forming a magnetic tunneling junction element over the metal line, depositing a silicon nitride cap layer conformally covering the magnetic tunneling junction element and the dielectric layer, depositing a tantalum containing cap layer conformally covering the silicon nitride cap layer, removing parts of the tantalum containing cap layer and the silicon nitride cap layer, and disposing a metal plug directly on the magnetic tunneling junction element.

Abstract: Provided is a semiconductor package including a stiffener. The semiconductor package comprises a circuit board, a semiconductor chip on the circuit board, and a stiffener around the semiconductor chip, wherein the stiffener includes a first metal layer, a core layer, and a second metal layer sequentially stacked.

Abstract: An integrated circuit assembly may be formed comprising an electronic substrate, a first and second integrated circuit device each having a first surface, a second surface, at least one side extending between the first and second surface, and an edge defined at an intersection of the second surface and the at least one side of each respective integrated circuit device, wherein the first surface of each integrated circuit device is electrically attached to the electronic substrate, an underfill material between the first surface of each integrated circuit device and the electronic substrate, and between the sides of the first and second integrated circuit devices, and at least one barrier structure adjacent at least one of the edge of first integrated circuit device and the edge of the second integrated circuit device, wherein the underfill material abuts the at least one barrier structure.

Abstract: A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.

Abstract: Semiconductor device includes a circuit substrate, a first semiconductor die and a package lid. The first semiconductor die is disposed on and electrically connected to the circuit substrate. The package lid extends over the first semiconductor die and is bonded to the circuit substrate. the package lid comprises a roof extending, a footing and an island. The roof extends along a first direction and a second direction perpendicular to the first direction. The footing is disposed at a peripheral edge of the roof and protrudes from the roof towards the circuit substrate along a third direction perpendicular to the first direction and the second direction. The island protrudes from the roof towards the circuit substrate, wherein the island is disconnected from the footing along the second direction, and the island is physically connected to the footing along the first direction.

Abstract: An Integrated Circuit (IC) package has a ferrite-dielectric shield between a planar inductor coil and a semiconductor chip. The shield blocks Electro-Magnetic Interference (EMI) generated by currents in the inductor coil from reaching the semiconductor chip. The shield has a ferrite layer surrounded by upper and lower dielectric laminate layers to prevent electrical shorts. The center end of the inductor coil connects to the semiconductor chip through a center post that fits through an opening in the shield that is over the air core center of the inductor coil. The center post can connect to a die attach pad that the semiconductor chip is mounted to. Bonding wires connect pads on the semiconductor chip to lead-frame pads on lead-frame risers that end at external package connectors. The outer end of the inductor coil connects to lead-frame outer risers also having external package connectors such as pins or bonding balls.

Abstract: A semiconductor package comprising a package substrate that has a recessed portion on a top surface thereof, a lower semiconductor chip in the recessed portion of the package substrate, an upper semiconductor chip on the lower semiconductor chip and the package substrate and having a width greater than that of the lower semiconductor chip, a plurality of first bumps directly between the package substrate and the upper semiconductor chip, and a plurality of second bumps directly between the lower semiconductor chip and the upper semiconductor chip. A pitch of the second bumps is less than that of the first bumps.

Abstract: Thermal heat spreaders and/or an IC die with solderable thermal structures may be assembled together with a solder array thermal interconnects. A thermal heat spreader may include a non-metallic material and one or more metallized surfaces suitable for bonding to a solder alloy employed as thermal interface material between the heat spreader and an IC die. An IC die may include a metallized back-side surface similarly suitable for bonding to a thermal interconnect comprising a solder alloy. Metallization on the IC die and/or heat spreader may comprise a plurality of solderable structures. A multi-chip package may include multiple IC die having different die thickness that are accommodated by a z-height thickness variation in the thermal interconnects and/or the solderable structures of the IC die or heat spreader.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes providing a substrate for an interposer, and forming a conductive interconnect structure in and on the substrate for connecting a group of selected IC dies. The method includes forming warpage-reducing trenches in non-routing regions of the interposer, wherein the warpage-reducing trenches are sized and positioned based on a warpage characteristic to reduce the warpage of the chip package structure. The method also includes depositing a warpage-relief material in the warpage-reducing trenches according to the warpage characteristic to reduce the warpage of the chip package structure, and bonding the group of selected IC dies to the interposer to form a chip package structure.

Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, a signal isolator IC package comprises a leadframe including a die paddle having a first surface to support a die and an exposed second surface. A die is supported by a die paddle wherein a width of the second surface of the die paddle is less than a width of the die.

Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a gate structure and a temperature sensitive component. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The first electrode, the second electrode and the gate structure are disposed on the second nitride semiconductor layer. The temperature sensitive component is disposed external to a region between the gate structure and the first electrode along a first direction in parallel to an interface of the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract: A wafer stack structure includes an interlayer, a first wafer, and a second wafer. The interlayer has a first surface and a second surface opposite to the first surface. The intermediate layer includes a dielectric material layer and a redistribution layer embedded in the dielectric material layer. The first wafer is disposed on the first surface of the interlayer. The second wafer is disposed on the second surface of the interlayer. The second wafer is electrically connected to the first wafer through the redistribution layer of the interlayer.

Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.