Patents Examined by Errol V Fernandes
  • Patent number: 11955517
    Abstract: A semiconductor device can include a field insulation layer including a planar major surface extending in first and second orthogonal directions and a protruding portion that protrudes a particular distance from the major surface relative to the first and second orthogonal directions. First and second multi-channel active fins can extend on the field insulation layer, and can be separated from one another by the protruding portion. A conductive layer can extend from an uppermost surface of the protruding portion to cross over the protruding portion between the first and second multi-channel active fins.
    Type: Grant
    Filed: November 15, 2020
    Date of Patent: April 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Hee-Soo Kang, Sang-Pil Sim, Soo-Hun Hong
  • Patent number: 11955401
    Abstract: A package structure includes a semiconductor device and an adhesive pattern. The adhesive pattern surrounds the semiconductor device, wherein an angle ? is formed between a sidewall of the semiconductor device and a sidewall of the adhesive pattern, 0°<?<90° wherein the adhesive layer has a first opening misaligned with a corner of the semiconductor device closest to the first opening.
    Type: Grant
    Filed: March 13, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hui Wang, Der-Chyang Yeh, Shih-Peng Tai, Tsung-Shu Lin, Yi-Chung Huang
  • Patent number: 11948927
    Abstract: A semiconductor die includes a structural body that has a power region and a peripheral region surrounding the power region. At least one power device is positioned in the power region. Trench-insulation means extend in the structural body starting from the front side towards the back side along a first direction, adapted to hinder conduction of heat from the power region towards the peripheral region along a second direction orthogonal to the first direction. The trench-insulation means have an extension, in the second direction, greater than the thickness of the structural body along the first direction.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: April 2, 2024
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Davide Giuseppe Patti, Mario Antonio Aleo
  • Patent number: 11942384
    Abstract: A semiconductor package including a leadframe has a plurality of leads, and a semiconductor die including bond pads attached to the leadframe with the bond pads electrically coupled to the plurality of leads. The semiconductor die includes a substrate having a semiconductor surface including circuitry having nodes coupled to the bond pads. A mold compound encapsulates the semiconductor die. The mold compound is interdigitated having alternating extended mold regions over the plurality of leads and recessed mold regions in between adjacent ones of the plurality of leads.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: March 26, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Makoto Shibuya, Masamitsu Matsuura, Kengo Aoya, Hideaki Matsunaga, Anindya Poddar
  • Patent number: 11935836
    Abstract: A semiconductor device includes a bridge and a first integrated circuit. The bridge is free of active devices and includes a first conductive connector. The first integrated circuit includes a substrate and a second conductive connector disposed in a first dielectric layer over the substrate. The second conductive connector is directly bonded to the first conductive connector. The second conductive connector includes conductive pads and first conductive vias and a second conductive via between the conductive pads. The second conductive via is not overlapped with the first conductive vias while the first conductive vias are overlapped with one another. A vertical distance between the second conductive via and the first conductive connector is larger than a vertical distance between each of the first conductive vias and the first conductive connector, and a sidewall of the first dielectric layer is substantially flush with a sidewall of the substrate.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: March 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hung Lin, An-Jhih Su, Der-Chyang Yeh, Shih-Guo Shen, Chia-Nan Yuan, Ming-Shih Yeh
  • Patent number: 11935855
    Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 19, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Jen Wang, Yi Dao Wang, Tung Yao Lin
  • Patent number: 11929262
    Abstract: A stack package and a method of manufacturing the stack package are provided. The method includes: attaching a first semiconductor device onto a first surface of a first package substrate; attaching a molding resin material layer onto a first surface of a second package substrate; arranging the first surface of the first package substrate and the first surface of the second package substrate to face each other; compressing the first package substrate and the second package substrate while reflowing the molding resin material layer; and hardening the reflowed molding resin material layer.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-in Won, Jong-kak Jang, Dong-woo Kang, Do-yeon Kim
  • Patent number: 11929316
    Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 12, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongyoun Kim, Eungkyu Kim, Gwangjae Jeon
  • Patent number: 11929338
    Abstract: A method includes forming a first package component, and forming a first plurality of electrical connectors at a first surface of the first package component. The first plurality of electrical connectors are laid out as having a honeycomb pattern. A second package component is bonded to the first package component, wherein a second plurality of electrical connectors at a second surface of the second package component are bonded to the first plurality of electrical connectors.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shenggao Li
  • Patent number: 11923259
    Abstract: A package structure includes a package substrate, a first semiconductor package and a second semiconductor package, an underfill material, a gap filling structure and a heat dissipation structure. The first semiconductor package and the second semiconductor package are electrically bonded to the package substrate. The underfill material is disposed to fill a first space between the first semiconductor package and the package substrate and a second space between the second semiconductor package and the package substrate. The gap filling structure is disposed over the package substrate and in a first gap laterally between the first semiconductor package and the second semiconductor package. The heat dissipation structure is disposed on the package substrate and attached to the first semiconductor package and the second semiconductor package through a thermal conductive layer.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pu Wang, Li-Hui Cheng, Szu-Wei Lu, Tsung-Fu Tsai
  • Patent number: 11908833
    Abstract: A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: February 20, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Enyong Tai, Hem P. Takiar, Li Wang, Hong Wan Ng
  • Patent number: 11901349
    Abstract: Embodiments of the present disclosure provide a semiconductor package. In one embodiment, the semiconductor package includes a first integrated circuit die having a first circuit design, and the first integrated circuit die comprises a first device layer and a first interconnect structure. The semiconductor package also includes a second integrated circuit die having a second circuit design different than the first circuit design, and the second integrated circuit die comprises a second device layer and a second interconnect structure having a first side in contact with the first device layer and a second side in direct contact with the first interconnect structure of the first integrated circuit die. The semiconductor package further includes a substrate having a first side bonded to the first interconnect structure, wherein the second integrated circuit die is surrounded by at least a portion of the substrate.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Tang Hung, Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11901330
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
  • Patent number: 11881467
    Abstract: A semiconductor package includes a first connection structure having first and second surfaces and including a first redistribution layer, a first semiconductor chip disposed on the first surface and having a first connection pad electrically connected to the first redistribution layer, a second semiconductor chip disposed around the first semiconductor chip on the first surface and having a second connection pad electrically connected to the first redistribution layer, an interconnection bridge disposed on the second surface to be spaced apart from the second surface and connected to the first redistribution layer through a connection member to electrically connect the first and second connection pads to each other, and a second connection structure disposed on the second surface to embed the interconnection bridge and including a second redistribution layer electrically connected to the first redistribution layer.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: January 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jungho Shim, Han Kim, Chulkyu Kim
  • Patent number: 11876148
    Abstract: A nitride semiconductor light-emitting element includes: an n-side nitride semiconductor layer; a p-side nitride semiconductor layer; and an active layer between the n-side nitride semiconductor layer and the p-side nitride semiconductor layer. The active layer includes: one or more well layers comprising a first well layer that is nearest to the n-side nitride semiconductor layer, and one or more barrier layers comprising a first barrier layer between the first well layer and the n-side nitride semiconductor layer. The first barrier layer comprises a Si-doped InGaN barrier layer and an undoped GaN barrier layer in this order from the n-side nitride semiconductor layer side.
    Type: Grant
    Filed: March 5, 2021
    Date of Patent: January 16, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Takuya Okada
  • Patent number: 11869820
    Abstract: An integrated circuit (IC) includes a substrate including circuitry configured for a function, the circuitry including at least one stress sensitive circuit portion, with at least a portion of nodes in the circuitry electrically coupled to bond pads provided by a top metal layer. A metal wall that is ring-shaped is positioned above the top metal layer that is not electrically coupled to the circuitry. The stress sensitive circuit portion is with at least a majority of its area within an inner area of the substrate that is framed by the metal wall to provide a cavity.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: January 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Amit Sureshkumar Nangia, Sreenivasan Kalyani Koduri, Siva Prakash Gurrum, Christopher Daniel Manack
  • Patent number: 11869870
    Abstract: First and second contacts are formed on first and second wafers from disparate first and second conductive materials, at least one of which is subject to surface oxidation when exposed to air. A layer of oxide-inhibiting material is disposed over a bonding surface of the first contact and the first and second wafers are positioned relative to one another such that a bonding surface of the second contact is in physical contact with the layer of oxide-inhibiting material. Thereafter, the first and second contacts and the layer of oxide-inhibiting material are heated to a temperature that renders the first and second contacts and the layer of oxide-inhibiting material to liquid phases such that at least the first and second contacts alloy into a eutectic bond.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: January 9, 2024
    Assignee: SiTime Corporation
    Inventors: Paul M. Hagelin, Charles I. Grosjean
  • Patent number: 11869822
    Abstract: A semiconductor package includes a redistribution structure, a plurality of semiconductor devices, and a plurality of heat dissipation films. The plurality of semiconductor devices mounted on the redistribution structure. The plurality of heat dissipation films are respectively disposed on and jointly covering upper surfaces of the plurality of semiconductor devices. A plurality of trenches are respectively extended between each two of the plurality of heat dissipations and extended between each two of the plurality of semiconductor devices.
    Type: Grant
    Filed: July 23, 2021
    Date of Patent: January 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Po-Yuan Cheng, Pu Wang, Li-Hui Cheng
  • Patent number: 11862567
    Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: January 2, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Bruley, Jack O. Chu, Kam-Leung Lee, Ahmet S. Ozcan, Paul M. Solomon, Jeng-bang Yau
  • Patent number: 11864388
    Abstract: In a semiconductor device, a stack of alternating gate layers and insulating layers is formed. Channel structures are formed in an array region of the stack. A first staircase is formed at a first section of the stack. A second staircase is formed at a second section of the stack. A dummy staircase is formed at the first section and disposed between the first staircase and the second staircase. The dummy staircase includes dummy group stair steps descending in a second direction parallel to a plane defined by any one of the gate layers and the insulating layers, and dummy division stair steps descending in a third direction and a fourth direction parallel to the plane and perpendicular to the second direction. The third direction and the fourth direction are opposite to each other.
    Type: Grant
    Filed: January 19, 2023
    Date of Patent: January 2, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhong Zhang, Wenxi Zhou, Zhiliang Xia