Abstract: A semiconductor package is provided. The semiconductor package may include at least one semiconductor chip including a contact pad configured to conduct a current, a conductor element, wherein the conductor element is arranged laterally overlapping the contact pad and with a distance to the contact pad, at least one electrically conductive spacer, a first adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the contact pad, and a second adhesive system configured to electrically and mechanically connect the at least one electrically conductive spacer with the conductor element, wherein the conductor element is electrically conductively connected to a clip or is at least part of a clip, and wherein the spacer is configured to electrically conductively connect the contact pad with the laterally overlapping portion of the conductor element.

Abstract: A method is provided for forming an integrated circuit (IC) chip package structure. The method includes: providing an interposer having a front surface and a back surface, the interposer comprising a substrate, at least one routing region, and at least one non-routing region; forming at least one warpage-reducing trench in the at least one non-routing region, wherein the at least one warpage-reducing trench extends from the front surface of the interposer to a first depth, the first depth smaller than a thickness between the front surface and the back surface of the interposer; depositing a warpage-relief material in the at least one warpage-reducing trench; and bonding the group of IC dies to the front surface of the interposer.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: A circuit substrate structure includes a circuit substrate, at least two chips, and a bridge element. The circuit substrate has a first surface and a second surface opposite to each other. The chips are arranged in parallel on the first surface of the circuit substrate and electrically connected to the circuit substrate. The chips have active surfaces, back surfaces opposite to the active surfaces, and side surfaces connecting the active surfaces and the back surfaces. The chips include side circuits. The side circuits are arranged on the side surfaces and have first ends and second ends, the first ends extend to the active surfaces along the side surfaces, and the second ends extend to the back surfaces along the side surfaces. The bridge element is arranged on the back surfaces of the chips and electrically connected to the active surfaces of the chips through the side circuits.

Abstract: A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer to be spaced apart from each other, the semiconductor devices being electrically connected to the package substrate through the interposer, and a molding layer on the interposer covering the semiconductor devices and exposing upper surfaces of the semiconductor devices, the molding layer including at least one groove extending in one direction between the semiconductor devices, the groove having a predetermined depth from an upper surface of the molding layer.

Abstract: A semiconductor package includes a redistribution substrate having first and second surfaces opposing one another, a first semiconductor chip on the first surface of the redistribution substrate, a passive device and a metal post on the second surface of the redistribution substrate and electrically connected to the redistribution pattern, a second encapsulant encapsulating at least side surfaces of the passive device and the metal post, a second insulating layer on a lower surface of the metal post and a lower surface of the second encapsulant, and having an opening exposing at least a portion of the lower surface of the metal post, and a connection bump filling the opening of the second insulating layer and in direct contact with the lower surface of the exposed metal post, wherein the metal post has a height greater than a height of each of the redistribution pattern and the redistribution via.

Abstract: The present disclosure provides a chip interconnecting method, an interconnect device and a method for forming a chip interconnection package. The method comprises arranging at least one chipset on a carrier, each chipset including at least a first chip and a second chip. A contact surface (or diameter) of each of the first bumps is smaller than that of any of the second bumps. The method further comprises attaching an interconnect device to the first chip and the second chip, the interconnect device including first pads for bonding to corresponding bumps on the first chip and second pads for bonding to corresponding bumps on the second chip. Attaching the interconnect device includes aligning the plurality of first pads with the corresponding bumps on the first chip whereby the plurality of second pads are self-aligned for bonding to the plurality of second bumps.

Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.

Abstract: A package structure and a testing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The wiring structure includes at least one dielectric layer, at least one conductive circuit layer in contact with the dielectric layer, and at least one test circuit structure in contact with the dielectric layer. The test circuit structure is disposed adjacent to the interconnection portion of the conductive circuit layer. The first electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the wiring structure. The second electronic device is electrically connected to the first electronic device through the interconnection portion of the conductive circuit layer.

Abstract: An electronic module is disclosed. In one example, the electronic module includes a first substrate, a first dielectric layer on the first substrate, at least one electronic chip, which is mounted with a first main surface directly or indirectly on partial region of the first dielectric layer, a second substrate over a second main surface of the at least one electronic chip, and an electrical contacting for the electric contact of the at least one electronic chip through the first dielectric layer. The first adhesion layer on the first substrate extends over an area, which exceeds the first main surface.

Abstract: An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.

Abstract: An electronic package structure and a method for manufacturing the same are provided. The electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer.

Abstract: A method includes forming a first package component, and forming a first plurality of electrical connectors at a first surface of the first package component. The first plurality of electrical connectors are laid out as having a honeycomb pattern. A second package component is bonded to the first package component, wherein a second plurality of electrical connectors at a second surface of the second package component are bonded to the first plurality of electrical connectors.

Abstract: The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first electrode, a second electrode, a gate structure and a temperature sensitive component. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer and has a bandgap greater than that of the first nitride semiconductor layer. The first electrode is disposed on the second nitride semiconductor layer. The second electrode is disposed on the second nitride semiconductor layer. The gate structure is disposed on the second nitride semiconductor layer and between the first electrode and the second electrode. The temperature sensitive component is disposed external to a region between the gate structure and the first electrode along a first direction in parallel to an interface of the first nitride semiconductor layer and the second nitride semiconductor layer.

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.

Abstract: Material systems for source region, drain region, and a semiconductor body of transistor devices in which the semiconductor body is electrically insulated from an underlying substrate are selected to reduce or eliminate a band to band tunneling (“BTBT”) effect between different energetic bands of the semiconductor body and one or both of the source region and the drain region. This can be accomplished by selecting a material for the semiconductor body with a band gap that is larger than a band gap for material(s) selected for the source region and/or drain region.

Abstract: A semiconductor package may include a redistribution substrate including first and second surfaces opposite each other, a first semiconductor chip on the first surface, a first molding portion on a side surface of the first semiconductor chip, a second semiconductor chip between the first semiconductor chip and the redistribution substrate, a second molding portion between the redistribution substrate and the first molding portion and on a side surface of the second semiconductor chip, bump patterns between the second semiconductor chip and the redistribution substrate, and a mold via penetrating the second molding portion and electrically connecting the first semiconductor chip to the redistribution substrate. The redistribution substrate may include first and second redistribution patterns sequentially in an insulating layer. The mold via may contact the second redistribution pattern, and the bump patterns may contact the first redistribution pattern.

Abstract: Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Abstract: A power semiconductor device includes: a substrate; drain metal; a drift region; a base region; a gate structure; a first conductive type doped region contacting the base region on the side of the base region distant from the gate structure; a source region provided in the base region and between the first conductive type doped region and the gate structure; contact metal that is provided on the first conductive type doped region and forms a contact barrier having rectifying characteristics together with the first conductive type doped region below; and source metal wrapping the contact metal and contacting the source region.

Abstract: Methods and apparatus for a signal isolator having enhanced creepage characteristics. In embodiments, an isolator includes a leadframe having first and second die paddles each having opposed first and second surfaces, a first die supported by the first surface of the first die paddle, and a second die supported by the first surface of the second die paddle. The first and second die paddles are configured enhanced creepage characteristics.