Abstract: Systems and techniques that facilitate improved single-shot error mitigation for Clifford circuits are provided. For a Clifford circuit, various embodiments described herein can facilitate two-sided or one-sided Pauli checks. In various aspects, left-side Pauli operators of two-sided Pauli checks can be selected randomly without replacement, and right-side Pauli operators of two-sided Pauli checks can be identified via commutation identities respectively relating the Clifford circuit to the left-side Pauli operators. In various instances, Pauli operators of one-sided Pauli checks can be selected via commutation identities respectively relating the Clifford circuit to Z-type Paulis selected randomly without replacement. For either two-sided or one-sided Pauli checks, various embodiments described herein can involve implementation of interleaved SWAP gates, which can allow such two-sided or one-sided Pauli checks to be performed on linear nearest neighbor coupling topologies.

Abstract: In a memory system, receiver reference voltage adjustment per path provides the capability to adjust receiver reference voltages on a per path basis. Adjustment of receiver reference voltages for the memory device to an optimal receiver reference voltage per path is accomplished with dedicated mode registers and a local receiver voltage reference adjuster circuit in the memory device for each data path. The optimal receiver reference voltage is determined during training based on selected feedback per path from the memory device. The dedicated mode registers contain adjustment values that were previously programmed during training, and include adjustments steps to add to or subtract from a global receiver reference voltage for all paths until reaching the optimal receiver reference voltage for a current path.

Abstract: Improved bit error correction for non-volatile memory can be implemented in multiple stages achieving improved correction capacity. As an example, bit error correction for a set of data can utilize a logic or a differential algorithm applied to one or more copies (N) of the set of data to produce a logic (or differential) output. An error correction code (ECC) can be applied to the logic (or differential) output to produce corrected data that corrects bit errors of the set of data, if any, up to a maximum for the ECC selected. An algorithm can be selected to address measured bit error rates or variations in bit error rates among binary bit states of a non-volatile memory.

Abstract: Various systems and methods are presented regarding applying a non-Clifford logical CCZ gate in a 2D topological code, e.g., a 2D Abelian code. A Kirigami cut and fold process is applied to an initial 3D quantum error-correcting code composed of three copies of 3D surface codes to reduce (cut) a qubit lattice to a hollow cube such that the cube is formed of surfaces comprising qubits. The CCZ is applied to the hollow cube, with the cube subsequently flattened (folded) from the 3D arrangement to a 2D code arrangement. A lattice surgery process can be performed to map/transfer the 2D code arrangement to an ancilla Kirigami code(s), whereupon the 2D code arrangement can be returned to a 2D surface code for further application of a logical Clifford gate, if so desired.

Abstract: A memory system includes a non-volatile memory and a memory controller. The memory stores data encoded with an error correction code for correcting errors of n (n is 3 or more) bits or less. The controller estimates the number of error bits by using syndromes calculated from a received word. When the number of error bits is two or three, the controller executes variable transformation on a variable of an error locator polynomial corresponding to the number of error bits with a first value or a second value based on the syndromes. The controller also executes, with the first/second values, calculation of roots of a transformed polynomial obtained by converting the error locator polynomial. The controller obtains roots of the error locator polynomial by variable inverse transformation on the roots of the transformed polynomial and corrects the error of the error locations corresponding to the obtained roots.

Abstract: A shared decoder pool is susceptible to head-of-line blocking when the decoding of a given data block delays the decoding of other data blocks pipelined in the decoder. While the problem can be avoided by not using a pipeline operation, the benefits of pipelining would be lost. In one embodiment provided herein, the syndrome of an error pattern is calculated in parallel with data being written in an input buffer for the decoder. Parallelizing the syndrome calculation and the filling of the decoder's input buffer can avoid the head-of-line blocking problem noted above while still achieving the benefits of pipelining. In another embodiment, a similar technique is used in a bit error rate estimation scan (BES) operation. Other embodiments are provided.

Abstract: Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative bit flipping decoder. A codeword is received and one or more of the bits in the codeword are flipped in each of multiple iterations of bit flipping decoding using a first set of bit flipping rules. Each of the iterations includes a determination of a syndrome weight. In response to determining a count of iterations in which the syndrome weight increased satisfies a threshold, one or more of the bits in the codeword are flipped in a subsequent iteration using a second set of bit flipping rules that differs from the first set of bit flipping rules.

Abstract: This application is directed to error correction for data stored in a memory device. In response to a request to validate a block of data, the memory device identifies a set of check nodes corresponding to a set of variable nodes that represent the block of data. First check node values of the check nodes are determined based on the block of data, and stored in first registers. The memory device implements a plurality of iterations of error correction by flipping a subset of variable nodes successively during each iteration; determining second check node values of the check nodes; and updating the first check node values stored in the first registers based on the second check node values once in each of a first set of iterations and successively with flipping of each variable node in a second set of iterations following the first set of iterations.

Abstract: Techniques are provided for generating a physical test pattern that is framed within an Forward Error Correction (FEC)-encoded stream or sequence. Accordingly, in one embodiment, a method is provided that includes obtaining a physical layer test pattern for testing operation of a device; generating an FEC framed test pattern that embeds the physical layer test pattern into an FEC-encoded stream; and applying the FEC framed test pattern to the transceiver device to test physical layer operation of the device and to obtain FEC error statistics.

Abstract: Methods and systems for operation in a wireless communication system are provided. A first transmission may be initiated using at least a first portion of physical layer resources. A second transmission may be initiated using at least a second portion of the same physical layer resources. The first transmission may be any one of a puncturing transmission, interfering transmission, delay-sensitive transmission, or short transmission. The second transmission may be an on-going transmission or a long transmission.

Abstract: A device includes a receiver configured to receive a plurality of Error Correction Code (ECC) codewords transmitted from an external device through a channel including one or more lanes; an ECC decoder configured to generate a plurality of post ECC codewords by performing error correction with respect to the plurality of ECC codewords and generating a first cyclic redundancy check (CRC) codeword based on the plurality of post ECC codewords; a CRC checker configured to determine whether an error exists in the first CRC codeword; and a post ECC decoder configured to, when it is determined that the error exists in the first CRC codeword, generate a second CRC codeword by estimating a remaining error position based on error correction result information received from the ECC decoder and performing remaining error correction with respect to the plurality of post ECC codewords based on the remaining error position.

Abstract: What is proposed is a solution for processing errors in a sequence of bits, wherein the sequence of bits, in the error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined thereby, wherein an error syndrome is determined for the sequence of bits, wherein a link is determined between components of the error syndrome and parts of the H-matrix, and wherein two adjacent bits in the sequence of bits are corrected if the link adopts a predefined value.

Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

Abstract: Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.

Abstract: The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.

Abstract: Methods and apparatus for constructing polar codes are provided. A transmitter determines at least one set of parameters corresponding to data to be transmitted, and a set of sorting indices corresponding to bits of the data to be transmitted based on the set of parameters, the set of sorting indices indicating a position set of the bits to be transmitted. The transmitter polar encodes the data based at least on the set of parameters and the set of sorting indices to generate a coded block of the data, and transmits the coded block of the data.

Abstract: A memory module includes a plurality of first memory chips and a second memory chip. Raw data is stored in the plurality of first memory chips. Parity data generated based on the raw data is stored in the second memory chip. Each of the first memory chips and the second memory chip is configured to exchange data with a controller based on a burst length unit. The second memory chip stores a first parity data generated from the raw data by a first error correction method, and stores a second parity data generated from the raw data and the first parity data by a second error correction method.

Abstract: Embodiments provide a data encoding method, a data decoding method, and a related device. The method includes a transmitting end device that determines N data symbols at a same symbol location of N links of service data, where N is an integer greater than 1, and quantities of bits in all data symbols are the same. The transmitting end device performs forward error correction (FEC) encoding on the N data symbols to obtain a codeword, where the codeword includes the N data symbols and M overhead symbols, M is an integer greater than or equal to 1 and less than or equal to N, and a quantity of bits in each data symbol is the same as a quantity of bits in each overhead symbol. The transmitting end device sends the N data symbols through N service channels, and sends the M overhead symbols through M overhead channels.

Abstract: A system includes a write-data register and a read-data register, each clocked by a clock signal, and a first-in-first-out (FIFO) buffer coupled between the write-data register and the read-data register, the FIFO buffer including latches configured to store data. The system further includes glue logic with first, second, and third logic circuits configured to generate an internal write enable signal, an internal read valid signal, and an internal read enable signal based on an operational mode of the system. The system is configured to be selectively switched between a normal operational mode, where the latches are accessed for reading and writing by a read enable signal and write enable signal based on a read address signal and a write address signal, and a transition testing mode, where the latches are tested using the internal write enable signal, the internal read enable signal, and the internal read valid signal.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may start a timer after transmitting an uplink communication on a physical uplink shared channel to a base station using a configured grant. The UE may determine whether the uplink communication is acknowledged as received by the base station based at least in part on determining whether a downlink communication from the base station is detected within a time duration associated with the timer. Numerous other aspects are provided.