Patents Examined by Esaw T Abraham
  • Patent number: 11128316
    Abstract: Methods and apparatus for constructing polar codes are provided. A transmitter determines at least one set of parameters corresponding to data to be transmitted, and a set of sorting indices corresponding to bits of the data to be transmitted based on the set of parameters, the set of sorting indices indicating a position set of the bits to be transmitted. The transmitter polar encodes the data based at least on the set of parameters and the set of sorting indices to generate a coded block of the data, and transmits the coded block of the data.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: September 21, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Changlong Xu, Jian Li, Jilei Hou, Chao Wei
  • Patent number: 11119150
    Abstract: Methods and apparatus are disclosed for programming reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a computing host includes one or more processors configured to execute a supervisor process and two or more user processes and a single FPGA integrated circuit configured into a plurality of partitions. The partitions include a host logic partition that is accessible only to the supervisor process executing on the computing host, and two or more accelerator partitions. Each of the accelerator partitions is configured to include a virtual debug unit with a logic analyzer that collects logic signals generated by logic within the respective accelerator partition and sends debug data indicating values of the logic signals to one of the user processes. In some examples, the host logic partitions and/or the accelerator partitions can be independently reprogrammed of each other within their respective portions of the single FPGA.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 14, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Mark Bradley Davis, Christopher Joseph Pettey, Asif Khan, Islam Mohamed Hatem Abdulfattah Mohamed Atta
  • Patent number: 11115051
    Abstract: Systems and methods are provided for decoding a codeword encoded by a linear block code. A method may comprise performing a hard decision decoding on a codeword, determining which check nodes are satisfied and which check nodes are unsatisfied after the hard decision decoding, scheduling a check node processing order by moving at least one unsatisfied check node to be processed ahead of at least one satisfied check node and performing a soft decision decoding on the codeword according to the check node processing order.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: September 7, 2021
    Assignee: INNOGRIT TECHNOLOGIES CO., LTD.
    Inventors: Yuan-mao Chang, Jie Chen, Chung-Li Wang
  • Patent number: 11115155
    Abstract: Disclosed herein includes a system, a method, and a device for prioritizing packet retransmission. A transmitting device can insert, for each packet of a plurality of packets of a video frame, a sequence number indicative of an order of the corresponding packet among the plurality of packets, into a header of the corresponding packet according to an application layer protocol. The transmitting device can transmit to the receiving device, at a first level of priority, the plurality of packets including the corresponding inserted sequence numbers. The transmitting device can receive an identification of one or more packets to be retransmitted to the receiving device, the identification based on at least the inserted sequence numbers of the one or more packets. The transmitting device can retransmit the one or more packets at a second level of priority that is higher than the first level of priority.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: September 7, 2021
    Assignee: Facebook Technologies, LLC
    Inventors: Behnam Bastani, Xiaoguang Wang, Gang Lu
  • Patent number: 11108411
    Abstract: The present application concerns an encoding device comprising a FC 11 configured to generate m FC-output-bit-sequences by executing m polar encoding steps upon m FC-input-bit-sequences that comprise frozen and unfrozen bits, wherein m?2. In an i-th polar encoding step of the m polar encoding steps at least one frozen bit is based on at least one unfrozen bit. The present application also concerns a decoding device comprising a processor configured to decode successively a polar-coded-bitstream comprising m-polar decoding steps, wherein m?2. In an i-th polar decoding step of the m polar decoding steps at least one frozen bit is based on at least one unfrozen bit. Further, the present application concerns also correspondingly arranged encoding and decoding methods.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: August 31, 2021
    Assignees: Huawei Technologies Duesseldorf GmbH, Technische Universit√§t M√ľnchen
    Inventors: Tobias Prinz, Peihong Yuan, Georg Boecherer, Gerhard Kramer, Onurcan Iscan, Ronald Boehnke, Wen Xu
  • Patent number: 11108408
    Abstract: A memory controller for use in a data storage device is provided. The memory controller includes a variable-node circuit and a check-node circuit. The check-node circuit is configured to obtain a codeword difference from the variable-node circuit, and calculate a syndrome according to the codeword difference.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: August 31, 2021
    Assignee: SILICON MOTION, INC.
    Inventor: Shiuan-Hao Kuo
  • Patent number: 11094391
    Abstract: A processor memory is stress tested with a variable list insertion depth using list insertion test segments with non-naturally aligned data boundaries. List insertion test segments are interspersed into test code of a processor memory tests to change the list insertion depth without changing results of the test code. The list insertion test segments are the same structure as the segments of the test code and have non-naturally aligned boundaries. The list insertion test segments include list insertion segments and load/store segments. The list insertion segments locate a current memory location using a fixed segment at a known location. The load/store segments load and store list elements in memory.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 17, 2021
    Assignee: International Business Machines Corporation
    Inventors: Manoj Dusanapudi, Shakti Kapoor, Nelson Wu
  • Patent number: 11088709
    Abstract: A polar code encoding method and apparatus are provided. The method includes: obtaining a basic sequence, where the basic sequence is a sequence obtained by sorting sequence numbers of polarized channels in descending order or ascending order of reliability, and a length of the basic sequence is L1; determining, based on a maximum encoding length L2 supported by a receiving device, a quantity M of segments of an information bit sequence whose length is N after encoding, where a quantity of bits in the information bit sequence before the encoding is K; and performing polar code encoding on the M segments based on the basic sequence. According to the polar code encoding method, during polar code construction, an encoding device needs to know only a reliability order of min(N/M, L1) polarized channels. In this way, storage overheads of a nested sequence can be effectively reduced, and online computing complexity can be reduced.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: August 10, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yourui Huangfu, Gongzheng Zhang, Chaolong Zhang, Rong Li, Jun Wang
  • Patent number: 11082159
    Abstract: A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 3, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Se-ho Myung, Kyung-joong Kim
  • Patent number: 11081150
    Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: August 3, 2021
    Assignee: SK hynix Inc.
    Inventors: Sang Gu Jo, Donggun Kim, Yong Ju Kim, Do-Sun Hong
  • Patent number: 11070316
    Abstract: An information processing method, an apparatus, a communications device, and a communications system are provided. The communications device is configured to: obtain a starting position in a buffer sequence W for an output bit sequence, and determine the output bit sequence from the buffer sequence W based on the starting position, where a value of the starting position is one element in {p0, p1, p2, . . . , pkmax?1}, 0?k<kmax, 0?pk<NCB, pk is an integer, k is an integer, NCB is a length of the buffer sequence W, kmax is an integer greater than or equal to 4, and there are two or more different neighboring intervals in {p0, p1, p2, . . . , pkmax?1}. A bit sequence for initial transmission or retransmission is properly determined, so that decoding performance of a communications device on a receive end after receiving the bit sequence is improved, a decoding success rate is enhanced, and a quantity of retransmission times is further reduced.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: July 20, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Liang Ma, Xin Zeng, Chen Zheng, Xiaojian Liu, Yuejun Wei
  • Patent number: 11069423
    Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: July 20, 2021
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, John Eric Linstadt, Paul William Roukema
  • Patent number: 11070314
    Abstract: An apparatus is provided which comprises at least one processor, at least one memory including computer program code, and the at least one processor, with the at least one memory and the computer program code, being arranged to cause the apparatus to at least perform generating a code block including information bits and parity bits, the parity bits being generated by performing a cyclic redundancy check on the information bits, determining the number of parity bits used in generating the code block based on an applied linear error correcting code base graph and/or based on the number of the information bits, and encoding the code block by using the applied linear error correcting code base graph.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: July 20, 2021
    Assignee: NOKIA SOLUTIONS AND NETWORKS OY
    Inventors: Keeth Saliya Jayasinghe Laddu, Yi Zhang, Jingyuan Sun
  • Patent number: 11061456
    Abstract: In one embodiment, an apparatus includes an interface for transmitting pulse power and data to a powered device over a wire pair and a controller for receiving input identifying power transitions in the pulse power and suspending data transmission during the power transitions. A method is also disclosed herein.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: July 13, 2021
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Chad M. Jones, Joel Richard Goergen, George Allan Zimmerman
  • Patent number: 11057056
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a plurality of modulation symbols, wherein the modulator is configured to map bits included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of each of the modulation symbols.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hong-sil Jeong, Kyung-joong Kim, Se-ho Myung
  • Patent number: 11057052
    Abstract: A data processing method is disclosed, and the method includes: receiving, by an encoding end, a to-be-encoded data block; obtaining, by the encoding end, a first mother code element for each first indication element in a first indication sequence based on an association relationship in which S=Q+B*N0 when B>0, and S=Q when B=0; and placing the first mother code element at a location of the first indication element in the first indication sequence to obtain a first mother code sequence.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: July 6, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Gongzheng Zhang, Rong Li, Jun Wang, Ying Chen, Huazi Zhang
  • Patent number: 11057057
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-joong Kim, Se-ho Myung, Hong-sil Jeong, Daniel Ansorregui Lobete, Belkacem Mouhouche
  • Patent number: 11057050
    Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-ho Myung, Hong-sil Jeong, Kyung-joong Kim
  • Patent number: 11044042
    Abstract: The present invention related to a 5G or pre-5G communication system to be provided to support a higher data transmission rate since 4G communication systems like LTE. The present invention relates to a method and an apparatus for encoding a channel in a communication or broadcasting system supporting parity-check matrices having various sizes are provided. The method for encoding a channel includes determining a block size of the parity-check matrix; reading a sequence for generating the parity-check matrix, and transforming the sequence by applying a previously defined operation to the sequence based on the determined block size.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 22, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seho Myung, Kyungjoong Kim, Min Jang, Hongsil Jeong
  • Patent number: 11042812
    Abstract: A method and associated systems for using direct sums and invariance groups to optimize the testing of partially symmetric quantum-logic circuits is disclosed. A test system receives information that describes the architecture of a quantum-logic circuit to be tested. The system uses this information to organize the circuit's inputs into two or more mutually exclusive subsets of inputs. The system computes a direct sum of a set of groups associated with the subsets in order to generate an invariance group that contains one or more invariant permutations of the circuit's inputs. These invariant permutations can be used to reduce the number of tests required to fully verify the circuit for all possible input vectors. Once one specific input vector has been verified, there is no need to test other vectors that can be generated by performing any one of the invariant permutations upon the previously verified vector.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 22, 2021
    Assignee: International Business Machines Corporation
    Inventor: Pawel Jasionowski