Abstract: An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Thk used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Thki may be calculated for each bit position. Thki and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

Abstract: Systems and methods of the present disclosure may be used to improve equalization module architectures for NAND cell read information. For example, embodiments of the present disclosure may provide for de-noising of NAND cell read information using a Multiple Shallow Threshold-Expert Machine Learning Models (MTM) equalizer. An MTM equalizer may include multiple shallow machine learning models, where each machine learning model is trained to specifically solve a classification task (e.g., a binary classification task) corresponding to a weak decision range between two possible read information values for a given NAND cell read operation. Accordingly, during inference, each read sample with a read value within a weak decision range is passed through a corresponding shallow machine learning model (e.g., a corresponding threshold expert) that is associated with (e.g., trained for) the particular weak decision range.

Abstract: Fuse logic is configured to selectively enable certain group of fuses of a fuse array to support one of column (or row) redundancy in one application or error correction code (ECC) operations in another application. For example, the fuse logic may decode the group of fuses to enable a replacement column (or row) of memory cells in one mode or application, and decodes a subset of the group of fuses to retrieve ECC data corresponding to a second group of fuses are encoded to enable a different replacement column or row of memory cells in a second mode or application. The fuse logic includes an ECC decode logic circuit that is selectively enabled to detect and correct errors in data encoded in the second group of fuses based on the ECC data encoded in the subset of fuses of the first group of fuses.

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

Abstract: An electronic circuit and method for self-diagnosis of a data memory (RAM) is described comprising/using a first error correction code unit (ECCGEN1) for generating an error correction code (ECCIN) from user data (DIN) to be written into the data memory (RAM). The electronic circuit is arranged to feed the user data (DIN) written into the memory and the related error correction code (ECCIN) into the error check unit (ECCCHK/CORR) in the write cycle when writing the user data and the related error correction code (ECCIN) into the data memory (RAM) to provide a Latent Fault flag in case of a determined difference between the error correction code (ECCIN) and the countercheck code (CCCIN) calculated from the user data (DIN) by the error check unit (ECCCHK/CORR).

Abstract: A memory system may include an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode, and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.

Abstract: An LDPC decoder receives channel information and performs a bit flipping algorithm to correct unsatisfied checks with respect to a parity matrix H. The threshold condition for determining whether to flip a bit is a function of the channel information itself. A threshold Thk used to evaluate the threshold condition may vary between iterations based on the number of iterations, number of bits flipped in the previous iteration, and number of unsatisfied checks. A threshold Thki may be calculated for each bit position. Thki and the threshold condition may be a function of whether bit position i was flipped in a previous iteration. A binning approach for parameters of the threshold condition may be used to reduce hardware complexity.

Abstract: The present application discloses a calibration data generation circuit and an associated method. The calibration data generation circuit includes: a first delay unit, having a first delay amount; and a first scan path, including: a first scan flip-flop, including: a scan data input terminal; a clock input terminal, arranged for receiving a clock signal; and an output terminal; and a second scan flip-flop, including: a scan data input terminal, coupled to the output terminal of the first scan flip-flop; a clock input terminal, arranged for receiving a delayed clock signal formed by the clock signal passing through the first delay unit; and an output terminal; wherein when the calibration data generation circuit operates, the first scan flip-flop and the second scan flip-flop are configured in a scan shift mode.

Abstract: A Reed-Solomon decoder circuit includes: a syndrome calculator circuit to compute syndrome values for a first codeword and a second codeword sequentially supplied to the syndrome calculator circuit, where last symbols of the first codeword overlap with first symbols of the second codeword during an overlap clock cycle between: a first plurality of non-overlap clock cycles during which the first codeword is supplied to the syndrome calculator circuit; and a second plurality of non-overlap clock cycles during which the second codeword is supplied to the syndrome calculator circuit; an error locator and error evaluator polynomial calculator circuit; an error location and error value calculator circuit; an error counter; and an error corrector circuit to correct the errors in the first codeword and the second codeword based on error counts and the error magnitudes computed by an error evaluator circuit.

Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.

Abstract: In a wireless local area network (WLAN) system, a transmission STA can transmit a PPDU via a 320 MHz channel, and a Medium Access Control (MAC) signal may be generated for the PPDU. The MAC signal may include puncturing pattern information and channel center frequency segment (CCFS) information for a 320 MHz band. The CCFS information may include a first CCFS field related to channel center frequency (CCF) information of a primary 160 MHz channel, and a second CCFS field related to CCF information of a 320 MHz channel.

Abstract: Disclosed is a network-based hyperdimensional system having an encoder configured to receive input data and encode the input data using hyperdimensional computing to generate a hypervector having encoded data bits that represent the input data. The network-based hyperdimensional system further includes a decoder configured to receive the encoded data bits, decode the encoded data bits, and reconstruct the input data from the decoded data bits. In some embodiments, the encoder is configured for direct hyperdimensional learning on transmitted data with no need for data decoding by the decoder.

Abstract: A memory device having a bit-flipping decoder. The decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. The decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.

Abstract: A plurality of computing devices are communicatively coupled to each other via a network, and each of the plurality of computing devices is operably coupled to one or more of a plurality of storage devices. Data communication is made more efficient by removing the need to copy data in the networking stack, using hardware accelerated end-to-end checksum calculation, and supporting transmission formatting of data and header for special cases.

Abstract: A processing device in a memory sub-system reads a sense word from a memory device and executes a plurality of parity check equations on corresponding subsets of the sense word to determine a plurality of parity check equation results. The processing device further determines a syndrome for the sense word using the plurality of parity check equation results and determines whether the syndrome for the sense word satisfies a codeword criterion. Responsive to the syndrome for the sense word not satisfying the codeword criterion, the processing device performs an iterative low density parity check (LDPC) correction process using a scaled bit flip threshold to correct one or more errors in the sense word.

Abstract: A method for product decoding within a data storage system includes receiving data to be decoded within a first decoder; performing a plurality of decoding iterations to decode the data utilizing a first decoder and a second decoder; and outputting fully decoded data based on the performance of the plurality of decoding iterations.

Abstract: The timing margin of various signal paths in an integrated circuit is monitored by components on the integrated circuit itself. Path margin monitor (PMM) circuits on the integrated circuit receive (a) functional signals propagating along signal paths in the integrated circuit, and (b) corresponding clock signals that are used to clock the functional signals. The PMM circuits output signals (PMM signals) which are indicative of the actual timing margins for the signal paths. For convenience, these will be referred to as path margins. A controller is also integrated on the integrated circuit. The controller controls the PMM circuits. It also receives and analyzes the PMM signals to monitor the path margins across the integrated circuit. Automated software is used to automatically insert instances of the PMM circuits into the design of the integrated circuit. The controller may also be automatically configured and inserted into the design.

Abstract: A dummy dual in-line memory module (DIMM) testing system based on boundary scan interconnect and a method thereof. A dummy dual in-line memory module functioning normally is used as a test fixture, a dummy dual in-line memory module under test is served as an unit under test (UUT), and the test fixture and the unit under test are inserted into a test device to electrically connect to each other, so that the test access port (TAP) device can perform boundary scan to control the test fixture to test the unit under test through signal pins, and check a test result based on a data signal collected from at least one boundary scan register. Therefore, the effect of improving testing convenience of the dummy DIMM can be achieved.

Abstract: The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.