Abstract: A dummy dual in-line memory module (DIMM) testing system based on boundary scan interconnect and a method thereof. A dummy dual in-line memory module functioning normally is used as a test fixture, a dummy dual in-line memory module under test is served as an unit under test (UUT), and the test fixture and the unit under test are inserted into a test device to electrically connect to each other, so that the test access port (TAP) device can perform boundary scan to control the test fixture to test the unit under test through signal pins, and check a test result based on a data signal collected from at least one boundary scan register. Therefore, the effect of improving testing convenience of the dummy DIMM can be achieved.

Abstract: The technology relates to an encoding device, an encoding method, a decoding device, a decoding method, and a program enabling encoding with favorable transmission efficiency with a controlled running disparity. A calculation section divides inputted data into N or M bits to calculate a first running disparity of an N or M bit data string. A determination section determines whether the data string is inverted based on the first running disparity calculated by the calculation section and a second running disparity calculated therebefore. An addition section inverts or non-inverts the data string based on a determination result by the determination section to add a flag indicating the determination result for outputting. The determination section determines not to perform inversion when the data string is a control code. The addition section adds the flag assigned to the control code. The technology is applicable to a device communicating in an SLVS-EC specification.

Abstract: Systems, methods, and apparatuses of creating a repair token for a distributed ledger are provided. A method includes identifying an error in the distributed ledger via a computing system. The error is associated with a first block on the distributed ledger. The method further includes creating the repair token having content of the first block and a correction to the error via the computing system.

Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: The present invention related to a 5G or pre-5G communication system to be provided to support a higher data transmission rate since 4G communication systems like LTE. The present invention relates to a method and an apparatus for encoding a channel in a communication or broadcasting system supporting parity-check matrices having various sizes are provided. The method for encoding a channel includes determining a block size of the parity-check matrix; reading a sequence for generating the parity-check matrix, and transforming the sequence by applying a previously defined operation to the sequence based on the determined block size.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for improving communication throughput despite periodic blockages. In some implementations, a method includes receiving, by a receiver and from a transmitter, code blocks transmitted according to a first set of communication parameters that includes one or more first interleaver parameters used to interleave information in the code blocks prior to transmission. Corrupted portions of at least some of the received code blocks are identified. A blockage duration and a blockage interval of a blockage of communication channel between the transmitter and the receiver are determined based on the corrupted portions of the received code blocks. A second set of communication parameters that includes one or more second interleaver parameters are determined based on the blockage duration and blockage interval.

Abstract: An LDPC encoding method and a system for error code detection. In the method and system, partial syndromes using a user portion and a low density parity check matrix are calculated, a parity portion of a codeword is calculated using the partial syndromes and using a quasi-cyclic matrix, the parity portion is generated by segment processing of the quasi-cyclic matrix, and the user portion and the parity portion are concatenated to complete the codeword.

Abstract: Storing and accessing information in a distributed data storage system includes: using erasure code, encoding a data block of the information to generate an encoded data block comprising both parity data and the data block, wherein by using the erasure code the data block may be reconstituted from a subset of the encoded data block, the subset comprising less than all of the data block; distributing, for storage, portions of the subset across a plurality of network storage locations such that the subset is not stored in its entirety at any one of the plurality of network storage locations; retrieving the distributed portions from the plurality of network storage locations; reconstituting the subset from the distributed portions that are retrieved; and using the erasure code, reconstituting the data block from the reconstituted subset of the encoded data block.

Abstract: A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

Abstract: A memory device, an error correction device and an error correction method thereof are provided. The error correction device includes a first error correction decoder and a second error correction decoder. The first error correction decoder performs at least one iteration of a first error correction operation on a data chunk, calculates a counting number of syndrome values equal to a set logic value generated in the at least one iteration of the first error correction operation, and generates a control signal according to the counting number. The second error correction decoder receives the control signal and determines whether to be activated to perform a second error correction operation on the data chunk or not according to the control signal. An error correction ability of the second error correction decoder is higher than an error correction ability of the first error correction decoder.

Abstract: Methods, systems, and devices for managing error control information using a register are described. A memory device may store, at a register, an indication of whether the memory device has detected an error included in or otherwise associated with data requested from a host device. The memory device may determine to store the indication based on whether a communication protocol is enabled or disabled, and whether an error control configuration is enabled or disabled. The host device may request information from the register of the memory device, and the memory device may output the indication of whether the error was detected in response to the request.

Abstract: A method includes identifying traits associated with a number of storage units of a storage network to produce identified traits. The method further includes determining a plurality of sets of storage pool traits based on the identified traits, where a first set of storage pool traits of the plurality of sets of storage pool traits has a common trait of the identified traits. The method further includes selecting a plurality of groups of storage units from the number of storage units based on the plurality of sets of storage pool traits. The method further includes selecting a storage unit from each of the plurality of groups of storage units in accordance with a selection approach to produce a storage set of selected storage units. The method further includes utilizing the storage set of selected storage units for storing data in the storage network.

Abstract: A transmitter apparatus and a receiver apparatus are provided. The transmitter apparatus includes: an encoder configured to generate a low density parity check (LDPC) by performing LDPC encoding; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol. The modulator maps a bit included in a predetermined group from among a plurality of groups constituting the LDPC codeword onto a predetermined bit in the modulation symbol.

Abstract: According to some embodiments, a method of operation of a wireless transmitter in a wireless communication network comprises: encoding a set of information carrying data bits u of length K with a linear outer code to generate a set of outer parity bits p along with the data bits u; interleaving the set of outer parity bits p and the data bits u using a predetermined interleaving mapping function that depends on the number of data bits K and is operable to distribute some bits of the set of parity bits p in front of some data bits u; and encoding the interleaved bits using a Polar encoder to generate a set of encoded bits x. Various interleaving mapping functions are disclosed.

Abstract: There is disclosed a method of operating a wireless device in a wireless communication network, the wireless device being triggered for aggregated transmission of first control information associated to a control channel, the aggregated transmission indicating a number R of retransmissions of the first control information to be performed. The method includes transmitting the first control information on a data channel based on a scaling parameter, the scaling parameter being based on the number R of retransmissions. The disclosure also pertains to related devices and methods.

Abstract: Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received and one or more of the plurality of bits in the codeword are flipped by a bit flipping decoder in each of a plurality of error correction iterations using a first plurality of bit flipping rules. In response to detecting a stall condition in the plurality of error correction iterations, a second plurality of bit flipping rules is selected. In each of one or more subsequent error correction iterations, the bit flipping decoder flips one or more of the plurality of bits in the codeword using the second plurality of bit flipping rules. The second plurality of bit flipping rules differs from the first plurality of bit flipping rules.

Abstract: A data scrambling method for controlling a code density according to an exemplary embodiment of the present disclosure includes receiving a plain code which is a code to be stored in the non-volatile memory device and a storage address at which the plain code is recorded; determining a rank corresponding to the plain code, using an ET table including appearance frequency rank information corresponding to individual plain code; calculating an adjustment rank corresponding to the plain code, using the rank and a random number that is generated based on the address of storage address; determining a cipher code corresponding to the appearance frequency rank of the plain code, using the adjustment rank and an ECC table including rank information determined by an objective function for individual cipher code; and storing the cipher code in the storage address.

Abstract: Methods, systems, and apparatuses detect and mitigate a stall condition in an iterative decoder. A codeword is received and one or more of the plurality of bits in the codeword are flipped by a bit flipping decoder in each of a plurality of error correction iterations. In response to detecting a stall condition in the plurality of error correction iterations, a maximum stop condition is increased. The maximum stop condition is a maximum iteration count threshold or a maximum decoding time threshold. The maximum stop condition triggers a stopping of the bit flipping decoder if the codeword is not decoded when the maximum stop condition is satisfied.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for improving communication throughput despite periodic blockages. In some implementations, a method includes receiving, by a receiver and from a transmitter, code blocks transmitted according to a first set of communication parameters that includes one or more first interleaver parameters used to interleave information in the code blocks prior to transmission. Corrupted portions of at least some of the received code blocks are identified. A blockage duration and a blockage interval of a blockage of communication channel between the transmitter and the receiver are determined based on the corrupted portions of the received code blocks. A second set of communication parameters that includes one or more second interleaver parameters are determined based on the blockage duration and blockage interval.