Patents Examined by Esaw T Abraham
  • Patent number: 10659321
    Abstract: A method and an electronic apparatus for converting debugging information to a binary form and providing more information in the same capacity memory are disclosed. A control method of the electronic apparatus which records debugging information, the method includes: obtaining debugging information using a source code; adding index information corresponding to the debugging information to the debugging information and storing the debugging information in a buffer; and converting a plurality of pieces of index information stored in the buffer to a binary file.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mun-seok Kim, Sang-mook Lim, Tomasz Duda
  • Patent number: 10656993
    Abstract: In various embodiments, an apparatus, system, and method may increase data integrity in a redundant storage system. In one embodiment, a request is received for data stored at a storage system having a plurality of storage elements, where one or more of the plurality of storage elements include parity information. A determination is made that one of the plurality of storage elements is unavailable, the unavailable storage element being a functional storage element and including at least a portion of the data. Responsive to the determination, the data is reconstructed based on at least a portion of the parity information and data from one or more of the plurality of storage elements other than the unavailable storage element; a response is provided to the request such that the response includes the reconstructed data.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: May 19, 2020
    Assignee: Unification Technologies LLC
    Inventors: Jonathan Thatcher, David Flynn, Joshua Aune, Jeremy Fillingim, Bill Inskeep, John Strasser, Kevin Vigor
  • Patent number: 10650902
    Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: May 12, 2020
    Assignee: Pure Storage, Inc.
    Inventors: Hari Kannan, Robert Lee, Yuhong Mao
  • Patent number: 10637511
    Abstract: Methods and systems for decoding raw data may include determining a sequence of a plurality of read-level voltages based on previous decoding data and executing a multi-stage decoding operation to decode raw data read from the plurality of memory cells using the determined sequence of the plurality of read-level voltages. Decoded data is returned from the multi-stage decoding operation upon completion of the multi-stage decoding operation and the previous decoding data is updated based on results of the multi-stage decoding operation.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: April 28, 2020
    Assignee: Western Digital Technologies, Inc
    Inventors: Jun Tao, Niang-Chu Chen
  • Patent number: 10623022
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: April 14, 2020
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10623024
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: April 14, 2020
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10614885
    Abstract: There are provided a microcontroller, a memory system having the same, and a method for operating the same. A memory system includes: a semiconductor memory performing a scanning operation on ROM data stored in a microcontroller in a test operation and outputting a result of the scanning operation as a status output signal; and a controller for determining whether an error exists in the ROM data, using the status output signal.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Byoung Sung You, Seung Hyun Chung, Jae Young Lee
  • Patent number: 10599581
    Abstract: A data storage device includes a nonvolatile memory device including an address map table in which a plurality of map segments including a plurality of logical-to-physical (P2L) entries are stored and a controller controlling the nonvolatile memory device. The controller includes a processor and a memory storing a map update module configured to be driven through the processor and perform map updating on the plurality of map segments. The map update module divides each of the map segments into a plurality of sub segments, updates a first sub segment as an updating target among the plurality of sub segments by loading the first sub segment into a map update buffer of the memory, and encodes second sub segments as a non-updating target among the plurality of sub segments and stores the encoded second sub segments in a page buffer of the nonvolatile memory device.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: March 24, 2020
    Assignee: SK hynix Inc.
    Inventor: Jee Yul Kim
  • Patent number: 10599514
    Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 24, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Saket Jalan, Indu Prathapan, Abishek Ganapati Karkisaval
  • Patent number: 10592299
    Abstract: A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: March 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yuji Kondo, Shinya Hiramoto, Yuichiro Ajima
  • Patent number: 10594437
    Abstract: The present disclosure relates to a receiving apparatus and a method therefor which are capable of decreasing a processing load and efficiently improving reproduction quality. A packet accumulating unit stores packets and packet type, and another packet information. A statistics information accumulating unit accumulates statistics information (e.g., an error ratio, performance (processing condition) of the receiving apparatus, a condition of a stream, and a condition of a buffer). A packet-correcting-method selecting unit selects a packet correcting method from a packet correction table generated in accordance with the packet information and packet identification/statistics information from the statistics information accumulating unit, and supplies a packet to be corrected to a packet correcting unit in a case where the packet in process is determined to be a target of correction. For example, the present disclosure can be applied to a communication system that transmits and receives data.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: March 17, 2020
    Assignee: SONY CORPORATION
    Inventors: Kazuhiro Ishigaya, Shinji Negishi, Michito Ishii, Takehito Watanabe, Yasuyuki Chaki, Noriaki Ooishi
  • Patent number: 10587371
    Abstract: There is disclosed a method of operating a user equipment in a radio access network. The method comprises transmitting feedback signaling utilizing a feedback resource range, the feedback resource range being determined based on a received feedback size indication and a received scheduling assignment indication, wherein the feedback resource range is a part of a signaling resource range configured to the user equipment for transmission.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 10, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Robert Baldemair, Stefan Parkvall
  • Patent number: 10587290
    Abstract: Methods are proposed herein to perform rate matching for polar codes via circular buffering of the polar encoded bits. Embodiments are directed to methods of operation of a transmitting node in a wireless system including performing polar encoding of a set of information bits in accordance with a polar sequence of length NB to thereby generate NB coded bits. The method can further include interleaving the coded bits to thereby provide an interleaved coded bit sequence, and storing the interleaved coded bit sequence into a circular buffer of length NB. According to certain embodiments, the method can further include extracting N coded bits for transmission from the circular buffer. N can be greater than, equal to, or less than NB.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 10, 2020
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Dennis Hui, Yufei Blankenship
  • Patent number: 10571520
    Abstract: A scan chain latch circuit, a method of operating a latch circuit in a scan chain, and a computer-readable medium having stored thereon a data structure defining a scan chain latch circuit for instantiation on a semiconductor die are disclosed. In an embodiment, the scan chain latch circuit comprises a first latch for holding one data value, a second latch for holding another data value, and a multiplexor. The one data value is applied to a first data input of the multiplexor and the another data value is applied to a second data input of the multiplexor. An alternating clock signal is applied to a select input of the multiplexor to control the output of the multiplexor, wherein the output of the multiplexor toggles between the two data values held in the two latches at a defined frequency.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: February 25, 2020
    Assignee: Internatioanl Business Machines Corporation
    Inventors: Dzmitry S. Maliuk, Franco Stellari, Alan J. Weger, Peilin Song
  • Patent number: 10572173
    Abstract: Elastic cloud storage (ECS) systems typically divide storage nodes into geographic or topological zones and implement various concepts that enable the system to be extremely efficient in terms of capacity management. Architectures detailed herein can improve ECS and other similar systems in terms of inter-zone data transfers and remote data caching without violating core concepts of an ECS system that enable efficient capacity management.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: February 25, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Mikhail Danilov, Grigorii Skripko
  • Patent number: 10564866
    Abstract: According to one aspect, bank-level fault management in a memory system is provided. The memory system includes a plurality of ranks, each rank including memory devices each having a plurality of banks. A first error is detected in a first bank number of a first memory device of a rank. The first bank number of the first memory device is marked with a bank-level chip mark. The bank-level chip mark isolates declaration of an error condition to the first bank number. A second error is detected in the first bank number of a second memory device of the rank. Access requests for the first bank number of the second memory device are steered to the non-faulty bank having the second bank number. A bank-level fault management action is performed based on the bank-level chip mark to accommodate the error condition by correcting the first error using an error-correcting code decoder.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy J. Dell, Girisankar Paulraj, Diyanesh B. Chinnakkonda Vidyapoornachary
  • Patent number: 10567002
    Abstract: Certain aspects of the present disclosure provide an efficiently decodable QC-LDPC code which is based on a base matrix, the base matrix being formed by columns and rows, the columns being dividable into one or more columns corresponding to punctured variable nodes and columns corresponding to non-punctured variable nodes. Apparatus at a transmitting side includes a encoder configured to encode a sequence of information bits based on the base matrix. Apparatus at a receiving side configured to receive a codeword in accordance with a radio technology across a wireless channel. The apparatus at the receiving side includes a decoder configured to decode the codeword based on the base matrix.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: February 18, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yurii Sergeevich Shutkin, Pavel Anatolyevich Panteleev, Aleksey Alexandrovich Letunovskiy, Elyar Eldarovich Gasanov, Gleb Vyacheslavovich Kalachev, Ivan Leonidovich Mazurenko
  • Patent number: 10564876
    Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seonghoon Woo, Soon Suk Hwang
  • Patent number: 10554227
    Abstract: A memory system configured to decode a data set may pause a convergence process to update reliability metric values. The memory system may utilize a positive feedback system that updates the reliability metric values by analyzing current a posteriori reliability metric values to calculate average estimated reliability characteristic values associated with a memory error model. The updates to the reliability metric values may provide increased error correction capability and faster decoding.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Eran Sharon, Alexander Bazarsky, Ariel Navon, Omer Fainzilber
  • Patent number: 10540104
    Abstract: A memory device includes a memory component that stores data and a processor. The processor may receive requests from a requesting component to perform a plurality of data operations, generate a plurality of packets associated with the plurality of data operations, and continuously transmit each of the plurality of packets until each of the plurality of packets are transmitted. Each of the plurality of packets after the first packet of the plurality of packets is transmitted on a subsequent clock cycle immediately after a previous packet is transmitted.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: January 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: J. Thomas Pawlowski