Abstract: A semiconductor device may be provided. The semiconductor device may be configured to shift storage positions of data and error information on the data to store the data into shifted storage positions based on the address signals having a certain combination being inputted a predetermined number of times.

Abstract: A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature. While the NVM array is heated to the target temperature, a current distribution is obtained by measuring a plurality of currents of a subset of NVM cells of the NVM array, each NVM cell of the NVM array is programmed to one of a logically high state or a logically low state, and first and second pass/fail (P/F) tests on each NVM cell of the NVM array are performed. A bit error rate is calculated based on the current distribution and the first and second P/F tests.

Abstract: Techniques related to improving power consumption of an LDPC decoder are described. In an example, the LDPC decoder uses a message passing algorithm between variable nodes and check nodes. A check node processing unit that generates check node to variable node messages implements a plurality of check node processing mode. Operation in each mode consumes a certain amount of power while providing a certain accuracy. Depending on a reliability of a variable node to check node message received by the check node processing unit, an appropriate check node processing mode is selected and used to generate a corresponding check node to variable node message. The reliability can be estimated for a set of variable node to check node messages based on, for instance, syndrome-related parameters.

Abstract: An apparatus may comprise an ECC circuit configured to receive read data from a memory cell array to correct, an error bit contained in a data portion of the read data responsive, at least in part, to a parity portion of the read data, to generate a plurality of first error determination signals and a plurality of second error determination signals. Each of the plurality of first error determination signals provided in common to n data terminals and corresponding to an associated one of burst data of m bits. Each of the plurality of second error determination signals provided in common to the burst data of m bits and corresponding to an associated one of the n data terminals. The error bit of the data portion of the read data is detected based, at least in part, on the first error determination signals and the second error determination signals.

Abstract: A method, an apparatus, and a system for data address management in non-volatile memory. Write data is allocated to each of a plurality of multi-level pages configured for storage on a page of a non-volatile memory array. A digest is associated with the write data of one multi-level page based on an attribute for that multi-level page. This attribute differs from the attributes of at least one of the other multi-level pages. An amount of redundancy data to be stored with write data on the multi-level page is reduced to account for the associated digest. A digest may be distributed among a plurality of ECC codewords of a multi-level page. The reduced redundancy data, the digest, and the write data for the multi-level page are stored on the page along with the write data for each of the other multi-level pages of the plurality of multi-level pages.

Abstract: A memory system having non-volatile media and a controller configured to process requests from a host system to store data in the non-volatile media or retrieve data from the non-volatile media. The non-volatile media has a set of memory units. The memory system stores an indicator indicating whether the memory system is operating in a user mode or a manufacturing mode. A defect manager of the memory system identifies a threshold based on the indicator, monitors an error rate in reading data from the non-volatile media and, in response to the error rate reaching the threshold, screens the non-volatile media for defective memory units.

Abstract: Systems, methods, and apparatuses of creating a repair token for a distributed ledger are provided. A method includes identifying an error in the distributed ledger, the error associated with a first block on the distributed ledger, creating a repair token including content of the first block and a correction to the error, digitally signing and timestamping the repair token, and publishing the repair token to a repair token ledger.

Abstract: Disclosed herein are systems and methods for forward packet recovery in a communication network with constrained network bandwidth overhead. In exemplary embodiments, a target byte protection ratio is determined. Error correcting frames are dynamically generated by a first processor such that error correcting information can be generated to approximate the target byte protection ratio. The data packets and error correcting information are then transmitted across one or more communication networks to a second processor. The second processor can use the error correcting information to regenerate or replace data packets missing or corrupted in transmission across one or more communication networks.

Abstract: The present technology relates to an error correction circuit. According to the present technology, an error correction circuit performing error correction encoding on a plurality of messages to be stored in a memory device includes a first error correction encoder and a second error correction encoder. The first error correction encoder generates a plurality of codewords by performing first error correcting encoding on each of the plurality of messages. The second error correction encoder performs a second error correction encoding operation by performing an exclusive OR operation on symbols of an identical column layer within the codewords. The second error correction encoder determines a data unit as a target of the second error correction encoding operation based on a use period of the memory device.

Abstract: A method includes receiving a write request for writing incoming data to a target memory line and, in response to the write request, comparing the incoming data with existing data in the target memory line to determine a number of a first type of state transition. The method further includes, in response to determining that the number of the first type of state transition for the write request exceeds a threshold, prior to writing the incoming data to the target memory line, storing adjacent data from each of a set of memory lines adjacent to the target memory line, and after writing the incoming data to the target memory line, writing the stored data to the set of adjacent memory lines.

Abstract: The disclosure relates to a pre-5th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system, such as a long-term evolution (LTE). A method of a receiving device in a communication system is provided. The method includes receiving a signal, and decoding the received signal based on a polar decoding scheme which is based on a successive cancellation (SC) scheme to estimate an information sequence, wherein, in the polar decoding scheme, a second number of parity bits among a first number of parity bits of an outer code included in an input bit sequence to a polar encoder are used in an error detection operation, and a third number of parity bits among the first number of parity bits are used in an error correction operation.

Abstract: Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword has bits from defective bit locations and non-defective bit locations. A syndrome of a current copy of the codeword is determined. Channel information for non-defective bit locations is determined using the current copy of the codeword and the received codeword from the memory device. Energy function values are determined for bits of the codeword using the syndrome of the current copy. Determining the energy function values includes using the channel information for bits in non-defective bit locations and omitting channel information for bits in defective bit locations. One or more bits of the codeword are flipped in response to the energy function values for the one or more bits satisfying a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract: A system is provided to receive, by a controller, a first request to read a first page of data stored in a storage device which comprises a plurality of non-volatile memory units. The system accumulates, by a calculation module, a syndrome associated with the first page of data to obtain a syndrome weight. In response to determining that the syndrome weight is less than a predetermined threshold, the system writes, by the controller, the first page of data to a destination page of the storage device. In response to determining that the syndrome weight is greater than the predetermined threshold and that a current number of retries is less than a predetermined number: the system executes a retry process between the calculation module and a data flip engine of the controller to update the syndrome weight; and the system increments the current number of retries.

Abstract: A hard decoder includes an input data handler that receives and rearranges a low-density parity-check (LDPC) codeword, and a variable node updater that iteratively updates the rearranged LDPC codeword to generate an updated LDPC codeword during each decoding iteration of the rearranged LDPC codeword. The hard decoder further includes a syndrome generator that generates a syndrome vector associated with the updated LDPC codeword of each decoding iteration. During each decoding iteration, the rearranged LDPC codeword is updated based on a threshold value and the syndrome vector associated with the updated LDPC codeword of a previous decoding iteration and a validity of the updated LDPC codeword of the previous decoding iteration. The hard decoder further includes an output data handler that extracts a message from the updated LDPC codeword that is valid and outputs the extracted message.

Abstract: In a general aspect, information is encoded in data qubits in a three-dimensional device lattice. The data qubits reside in multiple layers of the three-dimensional device lattice, and each layer includes a respective two-dimensional device lattice. A three-dimensional color code is applied in the three-dimensional device lattice to detect errors in the data qubits residing in the multiple layers. A two-dimensional color code is applied in the two-dimensional device lattice in each respective layer to detect errors in one or more of the data qubits residing in the respective layer.

Abstract: A semiconductor memory device includes a resistive change memory device including a control circuit block and a plurality of memory decks electrically connected with the control circuit block. The semiconductor memory device includes a pattern generation block, a position correction block and a position decision block. The pattern generation block receives a row address, a column address and a deck selection signal to generate a plurality of pattern generation signals to select a plurality of memory cells in the memory deck in various patterns. The position correction block receives a temporary code for classifying the memory cells into a temporary near cell region and a temporary far cell region and for reflecting a position of the memory deck in the temporary code to output a correction code.

Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic. A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.

Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

Abstract: Methods and systems are described for obtaining a plurality of information bits, and responsively partitioning the obtained plurality of information bits into a plurality of subsets of information bits, generating a plurality of streams of forward error correction (FEC)-encoded bits using a plurality of FEC encoders receiving respective subsets of the plurality of subsets of information bits, providing the plurality of streams of FEC-encoded bits to a plurality of sub-channel encoders, each sub-channel encoder receiving a respective stream of FEC-encoded bits from a different FEC encoder of the plurality of FEC encoders for generating a set of codewords of a vector signaling code, and wherein sequential streams of FEC-encoded bits from a given FEC encoder are provided to different sub-channel encoders for each successively generated set of codewords, and transmitting the successively generated sets of codewords of the vector signaling code over a multi-wire bus.