Abstract: The semiconductor device has more-significant global data lines and less-significant data lines hierarchically formed, and switches for controlling the more-significant global data lines and the less-significant data lines to be connected each other. In addition, the semiconductor device has the unit for precharging the global data lines independently of the data lines.

Abstract: The semiconductor memory device is improved so as to be simplified and to cope with a high speed CPU by allowing the CPU and the memory device to be controllable by only a single clock. The address control sections are operated on the basis of a monoperiod clock signal CLK and a group of control signals. The column address is applied to a plurality of divided memory cell arrays, respectively, so that the memory cell arrays can be interleaved with each other. The input and output buffers controlled by the input and output control section 1 are operated in pipeline processing, to increase the access speed of data read from or written in the memory cell arrays 17 and 18.

Abstract: A fully parallel CCD memory chip of N address lines which detects in just one clock cycle, a perfect match between an input pattern and any of a plurality of stored patterns and also detects in less than (N+1)-comparison cycles and still just one XOR operation, the best matching in case a perfect one does not exist. The chip disclosed herein has a fully parallel architecture in which an input word is compared to all stored words at one time. A preferred embodiment of the invention uses a four phase CCD, wherein each stored word occupies one row of the CCD and each such bit of each such word occupies two cells. Where perfect matches exist, only one comparison clock cycle is needed to compare the input word with all stored words and where there is no perfect match, the best match will be detected on a subsequent comparison pulse. Charge packets represent binary words generated by external pulses that are applied to the chip through data input lines and then are compared to the data applied to the address lines.

Abstract: A current sensing, cascadable differential amplifier has a special bias circuit that provides a low impedance input and a high impedance output, whereby plural stages may be connected in cascade. Optionally, active current sources are used as pull-ups for the data lines, to increase the output impedance and improve the data line common mode level. The amplifier performs as a current sensing sense amplifier in a large scale, fast access semiconductor memory and in this application, the memory does not need equalizing clock signals, nor is the access time slowed materially in the plural cascade stages.

Abstract: An apparatus includes a constant voltage generator for generating a voltage based on a difference between threshold voltages of two MOS transistors, and a voltage sampling device for sampling the output voltage of the constant voltage generator circuit, wherein the voltage sampling device samples the output voltage of the constant voltage generator before an electric source switch for the constant voltage generator is turned off.

Abstract: In a memory, a zone descriptor contains authorizations to act which may pertain to actions of reading, writing and erasure and which concerns memory words of a zone of the memory controlled by this descriptor. The zone descriptor also has an information element indicating the length of the memory zone by including the address of the next descriptor. An internal zone control signal is produced in order to store a mode of management of the memory zone and, an address corresponding to the end of the zone. The end of zone address is then compared with the addresses delivered by an address counter. A modification of the stored information is prompted when the end of a zone is reached.

Abstract: A circuit that allows an SRAM to automatically switch into low power mode before its power supply voltage input is brought to a lower voltage when the computer is turned off. The circuit includes a device that drives a chip enable input of the SRAM. The device is controlled by a signal indicating whether power is available to the computer system. If the system power is disconnected, the device asserts a low state to the chip enable input of the SRAM. The circuit also includes a device for gradually decreasing the voltage at the power supply voltage input of the SRAM from the system voltage down to the RTC/CMOS memory voltage, which is provided by a separate battery when the computer is shut off. The power supply input voltage is gradually decreased to allow the SRAM enough time to enter into its low power mode.

Abstract: An image observation device includes a two-dimensional image display element, a relay optical system for forming a real image of an image displayed on the two-dimensional image display element, an eyepiece optical system for forming a magnified image of the real image and bending the optical axis, and a supporting member for supporting the eyepiece optical system to be located directly before the eyes of the user. This arrangement makes it possible to provide the image observation device which is small in size and high in magnification for observation.

Abstract: An optical information storage apparatus includes an optical switch element and an optical fiber. The optical switch element receives an optical input and outputs an optical output only when the optical input is equal to or greater than a predetermined value. The optical fiber constitutes a first optical path. The optical fiber has at least one end face and receives an optical output emitted from the optical switch element through the at least one end face, guides the optical output, and emits an output beam, constituting the optical input, onto the optical switch element.

Abstract: A semiconductor memory device having a plurality of bits includes an input buffer for receiving external data, a first write circuit for inputting a first control signal, and an output of the input buffer, and outputting the result on a first data line. A second write circuit inputs a second control signal and the result from the first data line, and outputs another output on a second data line. In a data writing operation, the second control signal is used commonly for at least two bits. The first write circuit sets the first data line to a fixed potential state when the first control signal is effective. In response to the fixed potential status on the first data line, the second write circuit sets the second data line to a potential state in which the second control signal is disregarded. A write per bit mode operation is controlled by controlling the second write circuit through a first data line.

Abstract: This invention relates generally to slits used in optics that must be precisely aligned and adjusted. The optical slits of the present invention are useful in x-ray optics, x-ray beam lines, optical systems in which the entrance slit is critical for high wavelength resolution. The invention is particularly useful in ultra high vacuum systems where lubricants are difficult to use and designs which avoid the movement of metal parts against one another are important, such as monochrometers for high wavelength resolution with ultra high vacuum systems. The invention further relates to optical systems in which temperature characteristics of the slit materials is important. The present invention yet additionally relates to precision slits wherein the opposing edges of the slit must be precisely moved relative to a center line between the edges with each edge retaining its parallel orientation with respect to the other edge and/or the center line.

Abstract: A semiconductor memory device includes a memory cell array in which a number of sense amplifiers are provided, a plurality of segmented drive lines each connected to a group of sense amplifiers for driving the same, each of the segmented drive lines being formed of first and second drive line segments forming a pair, and a number of trunks for supplying electric power to the segmented drive lines. Each of the trunks includes a first conductor strip extending from a first side of the memory cell array toward a second side for connection to a plurality of the first drive line segments upon crossing the same, and a second conductor strip extending from the second side of the memory cell array toward the first side for connection to a plurality of the second drive line segments upon crossing the same.

Abstract: The invention provides fast generation of flag signals for devices such as a first-in first-out buffers by looking ahead and predetermining flag signals for future possible states of the device. Predetermining flag signals does not delay flag output because the required calculations are completed before the flag signal is needed. The flag signal can be changed when needed as quickly as a multiplexer can switch from an old flag signal to a predetermined flag signal. The switching time of a multiplexer is shorter than the comparator delays in prior art flag generators.

Abstract: A semiconductor device in which not only mask options of a mask ROM can be provided in the form of a PROM but the chip size can be reduced, and an electronic appliance using the same. The semiconductor device comprises a nonvolatile storage device (12) writable electrically, and switching circuits (18, 20) controlled on the basis of data stored in the nonvolatile storage device to perform wiring switching. Because wirings A, B1 and B2 are switched on the basis of data stored in the nonvolatile storage device, for example, optional functions of a one-chip micro computer can be provided in the form of a PROM by using the wiring switching.

Abstract: A band gap voltage reference circuit operates between a positive supply voltage and ground. The inputs to a difference amplifier of the band gap reference circuit are biased above the voltage drop of the base-emitter junctions of the band gap reference. The bias voltage is then subtracted from the difference amplifier output by a second difference amplifier. In addition, a bootstrap circuit assures a nonzero output from the first difference amplifier. Other embodiments wherein the band gap reference circuit is more generally a summing circuit are disclosed.

Abstract: A semiconductor memory device having a circuit for preventing the operation of a test mode includes a first terminal for receiving an externally applied high voltage exceeding a power supply potential, a second terminal for receiving an externally applied test mode signal and a high voltage detector for detecting that a high voltage signal has been applied through the first terminal. A test mode signal holding circuit is responsive to the high voltage detector and holds the test mode signal applied through the second terminal. A test circuit is responsive to the test mode signal held in the test mode signal holding circuit and performs a test in the semiconductor memory device. A disabling circuit is provided to disable the high voltage detector.

Abstract: Memory cell array includes a plurality of 2-port memory cells. A first row address decoder for decoding a first address signal to select a first word line included in any one of a plurality of word line groups, and a second row address decoder for decoding a second address signal to select a second word line included in any one of a plurality of word line groups are provided. A word line driving circuit receives output signals of first and second row address decoders to drive first and second word lines in accordance with a predetermined inhibit condition.

Abstract: A circuit (10) for storing and retrieving data is provided. Circuit (10) stores data on a data fuse (20). The values of the stored data may be established by comparing the data fuse (28) with a test fuse (22) using a storage and sensing circuit (12). The value of the data fuse (20) may be set by a fuse setting circuit (14). Additionally, a value may be substituted for the data fuse (20) using a flip flop (16) and an output logic circuit (18).

Abstract: A dynamic random access memory includes a plurality of DRAM cell units having a bit contact region and DRAM cells formed on an active region, wherein the DRAM cells each comprised of a transistor and a capacitor connected to the transistor are arranged symmetrically to the right and left sides in a bit contact connected with the active region to form the DRAM cell unit; and the DRAM cell units are arranged with a prescribed pitch in the direction of X and arranged in the direction of Y shifted with one third of the pitch toward the direction of X.

Abstract: A semiconductor memory device of alternately-activated open bit-line architecture is provided wherein paired bit lines extend from opposite sides of sense amplifiers that are arranged in one direction and every other bit line is activated through activation of a word line intersecting the bit lines. The sense amplifiers in the neighboring first and second rows alternate with each other in a staggering manner. The bit lines extending from the sense amplifiers of the first row in a first direction and the bit lines extending from the sense amplifiers in the opposite, second direction constitute a bit line group between the first and second rows. Word lines and dummy word lines intersect the bit line group.