Patents Examined by Eugene R. LaRoche
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Patent number: 5394267Abstract: A stereomicroscope comprising an objective lens, an afocal vari-focal optical system disposed coaxially with the objective lens, a pair of right and left imaging optical systems for imaging parallel rays emerging from the afocal vari-focal optical system, and right and left eyepiece lens systems for magnifying images which are formed by the right and left imaging optical systems.This stereomicroscope permits observing images with adequate stereoscopic impressions and can be relatively compact owing to a fact that the microscope satisfies the following condition (1):0.005 .ltoreq.AD.multidot..beta./f.sub.0 .ltoreq.0.Type: GrantFiled: June 29, 1993Date of Patent: February 28, 1995Assignee: Olympus Optical Co., Ltd.Inventor: Toyoharu Hanzawa
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Patent number: 5394359Abstract: The MOS cell with adjustable threshold voltage is a cell of the type with a memory that is electrically-erasable and programmable by storage of charges by tunnel effect in a floating gate. To obtain a circuit with adjustable threshold voltage, the cell is first of all "programmed" at zero so that all the charges that may be stored are removed and then it is "erased", with its source grounded, its drain taken to the high potential and its control gate taken to the potential desired for the threshold voltage V.sub.T of the circuit. At the end of this phase, the threshold voltage is adjusted. This device can be applied notably to circuits requiring precise voltage references in MOS technology, namely circuits of the detector or analog-digital converter type.Type: GrantFiled: September 14, 1992Date of Patent: February 28, 1995Assignee: Gemplus Card InternationalInventor: Jacek Kowalski
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Patent number: 5394358Abstract: A CMOS SRAM cell includes "true" and "false" NMOS word-line access transistors, "true" and "false" NMOS pull-down transistors, and "true" and "false" PMOS pull-down transistors arranged in a classical six-transistor SRAM electrical configuration. "True" and "false" inter-level interconnects of silicidable material provide for respective five-way connections among the transistors. The "true" inter-level interconnect connects: the drain of the "true" pull-up transistor, a gate level polysilicon conductor defining and connecting the gates of the "false" pull-up transistor and the "false" pull-down transistor, and a diffusion region defining and connecting the source of the "true" access transistor and the drain of the "true" pull-down transistor.Type: GrantFiled: March 28, 1994Date of Patent: February 28, 1995Assignee: VLSI Technology, Inc.Inventor: Tiao-Yuan Huang
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Patent number: 5394360Abstract: A non-volatile semiconductor memory providing a semiconductor substrate, drain and source regions which are provided on the surface of the semiconductor substrate and have a conductivity type different from that of the semiconductor substrate, a channel region formed between the drain and source regions, a floating gate (first gate electrode) for covering a part of the channel region. The drain region is self-aligned with the floating gate, and the source region is offset from the floating gate through an offset region by a constant distance. As a result, the drain and source regions are located asymmetrically with respect to the floating gate. A control gate (second gate electrode) substantially controls the surface potentials on the underside and in the vicinity of the floating gate. A selection gate (third gate electrode) controls the surface potential of the whole channel region including the offset region.Type: GrantFiled: June 18, 1993Date of Patent: February 28, 1995Assignee: Sharp Kabushiki KaishaInventor: Takahiro Fukumoto
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Patent number: 5394366Abstract: A DRAM device includes a read control circuit for inhibiting read out of one or more bits of a multi-bit data output from a plurality of memory cells in response to a bit designating signal for specifying the one or more bits. By arbitrarily setting the number of bits to be output from the DRAM device and combining that output with data from one or more additional memory devices, data of an arbitrary number of bits can be generated at a high speed.Type: GrantFiled: August 6, 1992Date of Patent: February 28, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takayuki Miyamoto
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Patent number: 5394372Abstract: A charge-pump system with an improved oscillation circuit. An electrically programmable non-volatile semiconductor memory device having the charge-pump system with the improved oscillation circuit includes a memory system equipped with a memory circuit having a non-volatile memory function, a oscillating circuit for generating an signal having a frequency which is increased in response to a decrease of a power supply voltage, and a charge-pump circuit which generates a voltage required to write data into or erase data from memory by charge-pumping the power supply voltage according to the signal generated by the oscillating circuit.Type: GrantFiled: March 26, 1993Date of Patent: February 28, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Tomoharu Tanaka, Riichiro Shirota
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Patent number: 5394371Abstract: In a mask ROM, for each of the memory cell groups, a load circuit connected to data lines for the respective memory cell group, a sense amplifier, and a switching circuit are provided. The switching circuit selectively connects one of the data lines which are simultaneously selected, to the sense amplifier. A data line for a dummy memory cell is also connected to the sense amplifier.Type: GrantFiled: December 7, 1993Date of Patent: February 28, 1995Assignee: Sharp Kabushiki KaishaInventor: Yasuhiro Hotta
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Patent number: 5394268Abstract: In an improved optical microscope for observing a luminescent specimen, the specimen is excited by a time-multiplexed series of standing wave fields. Then an image of the specimen is recorded and displayed. This specimen can be incrementally moved and additional images can be created and combined. Images of the specimen can also be created when there are nodes or antinodes at the focal plane of the microscope. These images can also be combined to produce an improved image of the specimen.Type: GrantFiled: February 5, 1993Date of Patent: February 28, 1995Assignee: Carnegie Mellon UniversityInventors: Frederick Lanni, D. Lansing Taylor, Brent Bailey
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Patent number: 5394353Abstract: A data compressor generates codewords representative of the location and length of a string match between an input data stream and a CAM array vocabulary table. A data decompressor looks up the codewords for a string match in its vocabulary table. The CAM array is arranged in a serpentine configuration to reduce track layout. A column priority encoder reverses the priority of alternate rows to maintain the logical flow through the CAM array. The CAM array uses a flipflop with a common control circuit to transfer and refresh data through the flipflop.Type: GrantFiled: September 20, 1993Date of Patent: February 28, 1995Assignee: Motorola, Inc.Inventors: Eugene B. Nusinov, James A. Pasco-Anderson
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Patent number: 5394364Abstract: In a memory readout circuit, a data register is provided for storing data bits of a word read out of a memory cell array. Connected to the data register is a transfer gate array which is equally divided into groups of first to k-th transfer gates. First to k-th data buffers are connected respectively to the first to k-th transfer gates of different groups. One of the groups of transfer gates is selected and the transfer gates of the selected group transfers first to k-th data bits of unit data from the data register to the first to k-th data buffers, respectively. From the data bits stored in the data buffers, i-th to k-th data bits (where i is in a range from 1 to k) are selected.Type: GrantFiled: March 31, 1994Date of Patent: February 28, 1995Assignee: NEC CorporationInventor: Takafumi Masuda
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Patent number: 5392248Abstract: The column-line short detection circuit of this invention includes a special test circuit that turns off wordlines (15), a N-channel transistor (23) for each column line (18), a decoder (19a) that uses only the least significant column address (20d) for input to the test circuit, and a sensor (SA) to detect current between shorted column lines (18). Because the column-line short detection circuit of this invention uses only the least significant address as input for column decoder (19a), it requires a very small number of transistors.Type: GrantFiled: October 26, 1993Date of Patent: February 21, 1995Assignee: Texas Instruments IncorporatedInventors: Phat C. Truong, Tim M. Coffman, Sung-Wei Lin, T. Damodar Reddy, Dennis R. Robinson
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Patent number: 5392252Abstract: A software programmable memory addressing system operates with multiple banks of DRAM chips. The DRAM chips in the different banks may be of different sizes and may be located physically in arrangements where the largest memory chips are not necessarily placed in the first memory bank. The system permits 256K, 1M, and 4M DRAMs to be supported separately, and in combinations of any two of the three types. An internal DRAM controller generates row address strobes (RAS) and column address strobes (CAS) which are supplied to a multiplexer switch bank for routing the RAS and CAS strobes to the physical DRAM banks according to a program set in a register used to control the operation of the multiplexers. Consequently, internally generated logical RAS and CAS signals are routed to the appropriate physical banks of DRAM to create a valid memory map, without requiring the physical arrangement of the banks of DRAMs in a pre-established order.Type: GrantFiled: November 13, 1990Date of Patent: February 21, 1995Assignee: VLSI Technology, Inc.Inventors: Charles R. Rimpo, Walter H. Potts, Joe A. Thomsen, Mitch A. Stones
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Patent number: 5392253Abstract: A nonvolatile semiconductor memory device is provided in which a negative voltage is applied to a gate electrode of a memory cell transistor during an erase mode. The memory device includes a row decoder circuit having an N-channel transistor connected to a word line. The N-channel transistor is provided on a P-type well region of a semiconductor substrate. A negative voltage is applied to the P-type well region during the erase mode, while ground potential is applied thereto during another modes.Type: GrantFiled: July 24, 1992Date of Patent: February 21, 1995Assignee: Kabushiki Kaisha ToshibaInventors: Shigeru Atsumi, Sumio Tanaka
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Patent number: 5392246Abstract: An area of a semiconductor chip, on which a memory is disposed, is divided into a plurality of memory blocks and redundant memory blocks, each memory block is divided into a plurality of unit arrays of columns for replacing, each redundant memory block is divided into a plurality of unit arrays of redundant columns, a plurality of memory cells are disposed in each unit array of columns for replacing and each unit array of redundant columns, a memory cell group in each unit array of columns for replacing is connected to a word line and a data line, a redundant memory cell group of each unit array of redundant columns is connected to a redundant word line and a redundant data line, a first data selection circuit for controlling data selection with respect to the unit array of redundant columns is disposed in each memory block, a second data selection circuit for controlling data selecting with respect to the unit array group of redundant columns is disposed in each redundant memory block, and a third data selecType: GrantFiled: March 3, 1994Date of Patent: February 21, 1995Assignee: Hitachi, Ltd.Inventors: Noboru Akiyama, Kinya Mitsumoto, Takashi Akioka, Seigoh Yukutake
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Patent number: 5392254Abstract: A semiconductor memory device having a memory cell array (MCA) composed of a plurality of memory cells arranged in a matrix pattern including a plurality of columns, a data register section provided with two first and second registers each having "a"-units of one-bit data register; a control section for selecting two sets of "a"-units of the column from a plurality of the columns for each "a"-cycles in accordance with inputted and read addresses, and for storing the "a" units of data of the selected 2 "a"-units of column in either one of the first and second registers alternately on the basis of a sequence of the read addresses; and a data output section for scanning and outputting data of the 2 "a"-units of the one-bit data register in sequence. Data of column bits more than the number of the registers can be accessed continuously in spite of the minimum register configuration. Further, the head column address can be selected freely.Type: GrantFiled: August 24, 1993Date of Patent: February 21, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Haruki Toda
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Patent number: 5392235Abstract: A semiconductor memory device includes a data line for receiving a voltage and an inverted data line having a voltage inverted relative to the voltage received by the data line; a first transistor and a second transistor for selecting a memory element for writing in data and reading out data through the data line and the inverted data line, respectively; two inverters, each inverter including a first p channel transistor and a first n channel transistor with the input and the output of the one inverter respectively connected to the output and the input of the other inverter and between either the source and the drain of the first transistor or the drain and the source of the second transistor; and a second p channel transistor connected in series to the first p channel transistor of one of the two inverters.Type: GrantFiled: May 19, 1993Date of Patent: February 21, 1995Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuharu Nishitani, Masao Takiguchi
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Patent number: 5392240Abstract: A semiconductor memory device comprises: a first bit line connected to a memory cell via a first switching element; a second bit line connected to a reference cell via a second switching element; a reference potential writing circuit for writing a reference potential in the reference cell; an equalizing circuit for equalizing the first and second bit lines in potential; a sense amplifier for detecting data in the memory cell on the basis of a difference in potential between the first and second bit lines; and a control section for reading data in the memory cell and data in the reference cell to the first bit line and the second bit line, respectively, and thereafter for activating the sense amplifier and roughly simultaneously turning off the second switching element.Type: GrantFiled: June 29, 1993Date of Patent: February 21, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Kazuyoshi Muraoka
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Patent number: 5392238Abstract: A semiconductor nonvolatile memory device according to the invention comprises a first cell block having with a current path and a plurality of memory cells, a second cell block having with a current path and a plurality of memory cells, the current path of the second cell block has an end connected to a corresponding end of the current path of the first cell block, a first line electrically connected to the other end of the current path of the first cell block, and a second line electrically connected to the other end of the current path of the second cell block. The first and second lines are made to operate a bit line and a source line, or vise versa, depending on which one of said cell blocks is selected for data retrieval.Type: GrantFiled: April 11, 1994Date of Patent: February 21, 1995Assignee: Kabushiki Kaisha ToshibaInventor: Ryouhei Kirisawa
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Patent number: 5392156Abstract: An optical device is composed of: a transparent base plate formed of a glass or a macromolecular resin; a first layer formed of a substance having a refractive index of 1.58 or higher; and a second layer formed of an amorphous transparent fluorocarbon resin having a refractive index of 1.35 or lower. The second layer is farther from the transparent base plate than the first layer from the transparent base plate. The first and second layer constitute a film for preventing reflection. Optionally, adhesive layers are provided between the transparent base plate and the first layer and between the first layer and the second layer. Further optionally, the surfaces of the transparent base plate and the first layer are treated in order to enhance adhesion between the contact surfaces.Type: GrantFiled: March 22, 1993Date of Patent: February 21, 1995Assignee: Canon Kabushiki KaishaInventors: Hiroaki Kumagai, Nagato Osano, Naoki Kobayashi
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Patent number: 5390045Abstract: A selectively variable window tinting system for limiting a passage of both visible light and radiative heat through an automobile window. Embodiments of the system include window glass assemblies which utilize photochromatic glass, electrochromatic glass, and a pair of spaced glass panes fillable with a tinted fluid. The latter embodiment also utilizes a plurality of differently tinted fluids which may be selectively injected between the glass panes to provide various amounts of tinting therein.Type: GrantFiled: July 9, 1993Date of Patent: February 14, 1995Inventor: Leroy A. Bernard, Jr.