Abstract: In one embodiment, the present invention includes a method for sending a connection request from a requestor endpoint to a target endpoint based on route information stored in the requestor endpoint, and receiving a connection confirmation from the target endpoint to confirm establishment of a peer-to-peer connection between the endpoints. The endpoints may be part of an Advanced Switching (AS) for Peripheral Component Interconnect (PCI) Express™ architecture, and in one embodiment a simple load store (SLS) protocol may be used for peer-to-peer communications in the AS environment. Other embodiments are described and claimed.

Abstract: An adaptive weighted arbitration algorithm that is user configurable is discussed. The arbitration logic and algorithm considers past arbitration history events and is dynamic to allow for losing bidders to increase their probability of being selected to access the resource based on an accumulator value and a weight value.

Abstract: A driver program for a multiprocessor subsystem includes an interrupt servicing routine (ISR) and a deferred procedure call (DPC). The ISR, invoked in response to an interrupt, determines whether any of the co-processors in the multiprocessor subsystem generated an interrupt. If one of the co-processors generated an interrupt, the ISR schedules the DPC for execution and disables sending of further interrupts from all of the co-processors. The DPC services pending interrupts from any of co-processors, then re-enables sending of interrupts from the co-processors.

Abstract: Data bus system and method are provided for controlling service engagements for bus users. At least one bus user provides services and other bus users use these services. A resource manager stores information about the available services and information about the service-providing bus users. The resource manager reserves a service from a providing bus user if the service can be used, and sends a response to a requesting bus user, allowing the requesting bus user to use the service from the providing bus user via the data bus. Information about the provided services is provided on the data bus via a standard interface by the bus users and a change in the provision of a service by a bus user is made available to the resource manager via the standard interface. The resource manager controls the service engagement on the basis of a priority information item.

Abstract: An interrupt control device for issuing interrupts to a central processing unit (CPU) includes an object acquiring unit for acquiring data or resource(s) for use by the CPU and an interrupt issuing unit for issuing interrupts to the CPU. The interrupt issuing unit issues each interrupt to the CPU before the object acquiring unit actually acquires the data or the resource, but the interrupt indicates that the data or the resource is available. The interrupt control device further includes a use delay unit for delaying the use of the data or resource by the CPU unit until the object acquiring unit acquires the data or the resource if the CPU which has received the interrupt requests the use of the data or the resource before the object acquiring unit acquires the data or the resource. By adjusting the exact timing of the issuance of the interrupt according to the actual delays experienced by the CPU, the overall delays associated with interrupt handling are minimized.

Abstract: A method, system and computer program product for creating and dynamically selecting an arbiter design within a data processing system on the basis of command history is disclosed. The method includes selecting a first arbiter for current use in arbitrating between requestors for a resource. During operation of said data processing system, an arbiter selection unit detects requests for the resource and selects a second arbiter in response to the detected requests for the resource.

Abstract: The signal integrity of a high speed heavily loaded multidrop memory bus is often degraded due the numerous impedance mismatches. The impedance mismatches causes the bus to exhibit a nonlinear frequency response, which diminishes signal integrity and limits the bandwidth of the bus. A compensating element, such as a capacitor which ties the bus to a reference plane (e.g., a ground potential), or an inductor wired in series with the bus, is located approximately midway between the memory controller and the memory slots. The use of the compensating element equalizes signal amplitudes and minimizes phase errors of signals in an interested frequency range and diminishes the amplitudes of high frequency signals which exhibit high degrees of phase error. The resulting bus structure has increased desirable harmonic content with low phase error, thereby permitting the bus to exhibit better rise time performance and permitting a higher data transfer rate.

Abstract: A method and system for wirelessly coupling a computer with a peripheral device. The peripheral device is initially docked to a docking port in the computer. Detecting the docking event, the computer then turns on the docked peripheral device and listens for identifiers from all peripheral devices within range of the computer, including the identifier for the peripheral device that is presently docked with the computer. The computer then instructs the docked peripheral device to turn off, thus preventing the docked peripheral device from broadcasting its identifier. By a process of deduction, the computer is able to identify the docked peripheral device. In a preferred embodiment, the docked peripheral device subsequently is wirelessly associated only with the computer to which that peripheral device was initially docked.

Abstract: An extended host controller test mode support is provided. In the example of USB host controllers, an enhanced host controller is provided to control the high-speed traffic. Further at least one companion host controller controls the full-speed and/or low-speed traffic. The enhanced host controller comprises a test circuit for controlling a USB transceiver macrocell to perform full-speed and/or low-speed test functions. The test functions may include a test-J function, a test-K function, a single-ended-zero test function, and the sending of test patterns.

Abstract: An integrated circuit 2 is provided with multiple bus masters 4, 6 and multiple bus slaves 8, 10, 12, communicating via a multi-channel communication bus. A separate write data channel, read data channel and write response channel are provided as well as a separate write address channel and a read address channel. The provision of a dedicated write response channel frees the read data channel to be more efficiently used for the transfer of read data. Transactions may be burst mode transactions with a single write response corresponding to the write transaction as a whole.

Abstract: A queue includes a plurality of containers. Each container includes a lock. Clients, possibly in a multiprocessor system, can simultaneously access the queue, each client locking only a single container as needed. The clients can access the queue without using a lock manager, directly accessing the container locks to determine whether the containers are in use.

Abstract: A method for preserving digital evidence of a computer misconduct, the method including the steps of: prior to the misconduct, installing an expansion card capable of retrieving and storing a memory image and register information from a digital electrical computer in which the expansion card is installed; connecting a switch to regulate the expansion card from a location other than the computer; at the time of the misconduct, using the switch to trigger the retrieving and storing of the memory image and the register information into the expansion card; and subsequent to the misconduct, extracting the expansion card to preserve digital evidence of the computer misconduct. This method can be carried out further by subjecting the memory image and register information from the expansion card with another computer to forensic analysis.

Abstract: A state indicating information setting circuit and a status bit setting circuit are responsive to detection of a predetermined state by a predetermined state detecting part for setting predetermined state indicating information and, then, appropriately resetting the detection state in the state detecting part.

Abstract: A GPRS replaceable module communication device includes a motherboard and a daughter board. The motherboard includes necessary components for enabling GPRS module operation and selecting module interface and setting, while the daughter board is a modularized add-on card whose function is determined by a replaceable module. The same GPRS motherboard can be used to accommodate different daughter boards for different functions, and the GPRS motherboard determines either to read the control data on the motherboard, or the control data on the daughter board by the insertion or removal of the daughter board.

Abstract: A data transmission device is used to forward data that have been received from a first device, and are intended for a second device, to the second device. The data transmission device described has a whole series of characteristics that allow the data that are to be transmitted to be transmitted very easily very quickly and which confer additional functions on the data transmission device.

Abstract: An online data migration method is provided for transferring data from a computer and an existing storage system using the conventional interface such as SCSI to a new storage system using SAN. The present method comprises the steps of disconnecting the connection between the computer and the first storage system with first interface protocol, connecting the computer to a switch connected to a second storage system with a second interface protocol through first protocol converter having protocol converting facility, connecting the switch to the first storage system through second protocol converter, and migrating data in the first storage system into the second storage system via the switch.

Abstract: A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.

Abstract: A method for operating an automation technology field device connected via a bus system with a superordinated unit and having an identifier identifying the type of the field device, at least one alternative identifier AKF1, which identifies a similar type of field device, is stored, in addition to an identifier KF1, in the field device F1. This alternative identifier AKF1 is transmitted, on query, to the superordinated unit PLC, when the superordinated unit fails to accept as valid the identifier KF1 transmitted in prior queries. In this way, a replacement of a field device is possible simply and quickly.

Abstract: Systems and methods are disclosed for arbitrating requests from a plurality of clients requesting access to a shared real-time resource. In one embodiment, a plurality of sub-clients are aggregated into an aggregate client. At the aggregate client, access requests from the sub-clients are arbitrated to generate an aggregate request. An aggregate deadline is determined and access requests from the aggregate client and other clients are arbitrated using the aggregate deadline as the deadline of the aggregate client. In one embodiment, a critical instant analysis of the system is performed using the aggregate deadline as the deadline of the aggregate client. In another embodiment, a block-out counter is employed at an aggregate client to regulate the rate at which the aggregate client provides access requests to the shared resource.

Abstract: A configurable switch that enables multiple CPUs to be connected to multiple I/O devices through a single switch. The switches can be cascaded to enable more CPUs and/or more I/O devices in the tree. The configuration is transparent to the enumeration of the bus and endpoint devices. A simple management input such as SMBus or hardware strapping is used to set up the assignation of devices to CPUs. Utilization of a manager and the PCI Express hot plug controller registers enable hot-plug reconfiguration of the device tree as devices a switched between CPUs via PCI buses within the switch.