Abstract: A USB-HUB device in which a request for a device connected to a port of the USB-HUB device may be executed by commonly using a serial interface engine of the HUB device has been disclosed. A USB-HUB device (1) may include a HUB address register (124), a HID address register (125), a first comparator (123), a second comparator (113), a virtual port control unit (18) and a HID request processing unit (131). A HID address register (125) may store a HID address. A first comparator (123) may compare a value of a HUB address register (124) with an address field of a supplied token packet. A second comparator (113) may compare a value of a HID address register (125) with an address field of the supplied token packet. A virtual port control unit (18) may indicate a status of a port to which a device (3) may be virtually connected. A HID processing unit (131) may perform a process in response to a request for the device (3).

Abstract: A method and an architecture for accessing hardware devices in a computer system and the chipset thereof are provided. A bi-directional two-wired serial interface, for instance, a system management bus (SMB), is configured to connect an I/O device, such as a local area network adapter, to a system controller such as a southbridge or a northbridge chipset. The I/O device which includes a SMB master controller serves as a SMB master device for generating a clock signal and transmitting a data signal defined by the SMB protocol to the system controller according to the clock signal. The system controller which includes a PCI master and a SMB slave controller serves as a SMB slave device for receiving commands and data bytes in the data signal from the SMB master device to drive the PCI master to access the register block of peripherals and system memory of the computer system.

Abstract: Disclosed are systems and methods for providing access to bus-mastered system resources comprising disposing a bus multiplexer between a first bus and a bus access arbiter, wherein the first bus is coupled to at least one system resource for which bus access is arbitrated by the bus access arbiter, and controlling the bus multiplexer to couple a second bus to the first bus thereby providing a link between the first bus and the second bus bypassing the bus access arbiter.

Abstract: Provided are a parameter generating circuit and a method of generating a parameter which decides priority of master blocks. An arbitration parameter generating circuit includes a counter, a short term arbitration parameter storage unit, a short term reference time measurement unit, a long term arbitration parameter control unit and a long term reference time measurement unit. The counter receives a request signal generated in order for a master block to occupy a system bus and a grant signal generated in order for an arbitrator to allow the master block to occupy the system bus, up-counts when the request signal is at a first logic level, down-counts when the grant signal is at the first logic level, and is reset in response to a predetermined short term reference time signal. The short term arbitration parameter storage unit receives and stores the counted signal as the short term arbitration parameter until the counter is reset in response to the short term reference time signal.