Abstract: A metal line includes a lower metal line formed on a semiconductor substrate. An insulation layer is formed on the semiconductor substrate having the lower metal line, and a metal line forming region exposing at least a portion of the lower metal line is defined in the insulation layer. A diffusion barrier is formed on a surface of the metal line forming region of the insulation layer and includes a WNx layer, a W—N—B ternary layer, and a Ti—N—B ternary layer. A wetting layer is formed on the diffusion barrier and is made of one of a Ti layer or a TiN layer. An upper metal line is formed on the wetting layer to fill the metal line forming region of the insulation layer.

Abstract: A light emitting diode (LED) for minimizing crystal defects in an active region and enhancing recombination efficiency of electrons and holes in the active region includes non-polar GaN-based semiconductor layers grown on a non-polar substrate. The semiconductor layers include a non-polar N-type semiconductor layer, a non-polar P-type semiconductor layer, and non-polar active region layers positioned between the N-type semiconductor layer and the P-type semiconductor layer. The non-polar active region layers include a well layer and a barrier layer with a superlattice structure.

Abstract: A light emitting module includes a semiconductor light source, a first lead with a bonding pad to which the light source is attached, and a second lead spaced from the first lead in a first direction contained in the plane of the first die bonding pad. The second lead includes a wire bonding pad connected to the light source via a wire. The module also includes a case formed with a space elongated in the first direction for accommodating the light source. The first lead includes an extension extending from the first die bonding pad, and a mounting terminal connected to the extension. The extension extends in a second direction that is perpendicular to the first direction and contained in the plane of the first die bonding pad. The mounting terminal extends perpendicularly to the second direction. The extension overlaps the light source in the first direction.

Abstract: In an electronic component soldering method of connecting a terminal provided on a flexible substrate to an electrode of a rigid substrate, after solder-mixed resin in which solder particles are mixed in thermosetting resin has been applied onto the rigid substrate so as to cover the electrode, the flexible substrate is put on the rigid substrate and heat-pressed, whereby there are formed a resin part that bonds the both substrates by thermosetting of the thermosetting resin, and a solder part which is surrounded by the resin part and has narrowed parts in which the peripheral surface is narrowed inward in the vicinity of the terminal surface and in the vicinity of the electrode surface. Hereby, the solder parts are soldered to the electrodes and the terminal at acute contact angles so that the production of shape-discontinuities which lowers fatigue strength can be eliminated.

Abstract: A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor region between adjacent trenches. A gate electrode is formed in each trench isolated from the semiconductor region by the gate dielectric. Well regions of a second conductivity type are formed in the semiconductor region. Source regions of the first conductivity type are formed in upper portions of the well regions. After forming the source regions, a salicide layer is formed over the gate electrode in each trench abutting portions of the gate dielectric. The gate dielectric prevents formation of the salicide layer over the mesa surfaces of the semiconductor region between adjacent trenches.

Abstract: A semiconductor device 1 includes a substrate 2 having on a main surface thereof a central area and a peripheral area which surrounds the central area and is exposed, a semiconductor layer 4 which is formed on the main surface of the substrate 2, is made of a material harder than the substrate 2, is in the shape of a mesa, and has a steep side over the exposed peripheral area, and an insulating film 12S provided on a side surface of the semiconductor layer 4.

Abstract: An object of the present invention is to provide a semiconductor device having a structure which can realize not only suppressing a punch-through current but also reusing a silicon wafer which is used for bonding, in manufacturing a semiconductor device using an SOI technique, and a manufacturing method thereof. The semiconductor device can suppress the punch-through current by forming a semiconductor film in which an impurity imparting a conductivity type opposite to that of a source region and a drain region is implanted over a substrate having an insulating surface, and forming a channel formation region using a semiconductor film of stacked layers obtained by bonding a single crystal semiconductor film to the semiconductor film by an SOI technique.

Abstract: A manufacturing method of a semiconductor device includes a film state underfill resin adhering step wherein film state underfill resin in a semi-cured state is adhered on the first surface of the board main body without forming a gap between the first surface of the board main body and the pad; a flattening step wherein an upper surface of the film state underfill resin is flattened; a chip connecting step wherein the semiconductor chip is pressed onto the upper surface of the film state underfill resin after the flattening step so that the semiconductor chip is flip chip connected to the pad; and an underfill resin forming step wherein the film state underfill resin is cured so that the underfill resin is formed between the semiconductor chip and the wiring board.

Abstract: InP epitaxial material is directly bonded onto a Silicon-On-Insulator (SOI) wafer having Vertical Outgassing Channels (VOCs) between the bonding surface and the insulator (buried oxide, or BOX) layer. H2O and other molecules near the bonding surface migrate to the closest VOC and are quenched in the buried oxide (BOX) layer quickly by combining with bridging oxygen ions and forming pairs of stable nonbridging hydroxyl groups (Si—OH). Various sizes and spacings of channels are envisioned for various devices.

Abstract: In a semiconductor light emitting device having a matrix of a plurality of bumps composed of one n-bump formed on an n-electrode layer and of a large number of p-bumps formed on p-electrode layers, the occurrence of a faulty junction after mounting can be suppressed by placement of the n-bump at center of the bump array, because the position at the center is most resistant to occurrence of stress after the mounting. Employment of such a configuration of bump array increases reliability of mounting thereof while improving uniformity of light emission intensity in the semiconductor light emitting device having an increased size.

Abstract: A heterojunction field-effect semiconductor device has a main semiconductor region comprising two layers of dissimilar materials such that a two-dimensional electron gas layer is generated along the heterojunction between the two layers. A source and a drain electrode are placed in spaced positions on a major surface of the main semiconductor region and electrically coupled to the 2DEG layer. Between these electrodes, a gate electrode is received in a recess in the major surface of the main semiconductor region via a p-type metal oxide semiconductor film and insulating film, whereby a depletion zone is normally created in the 2DEG layer, making the device normally off. The p-type metal oxide semiconductor film of high hole concentration serves for the normally-off performance of the device with low gate leak current, and the insulating film for further reduction of gate leak current.

Abstract: A memory device including a programmable resistive memory material is described along with methods for manufacturing the memory device. A memory device disclosed herein includes top and bottom electrodes and a multilayer stack disposed between the top and bottom electrodes. The multilayer stack includes a memory element comprising programmable resistive memory material and has a sidewall surface. An air gap is adjacent to the sidewall surface and self-aligned to the memory element.

Abstract: The outer peripheral portion of a substrate is provided with a first peripheral edge and a second peripheral edge. The first peripheral edge is provided on the edge portion of a first upper surface of the substrate on which a light-emitting diode element is mounted. The second peripheral edge is formed either on an extension of an imaginary line connecting an edge of the light-emitting facet of the light-emitting diode element and the first peripheral edge or inwardly of the extension. The second peripheral edge is located at a position where the first peripheral edge blocks direct light from the light-emitting diode element. This configuration prevents the second upper surface of the substrate provided between the first peripheral edge and the second peripheral edge from becoming deteriorated due to the direct light.

Abstract: An apparatus having a substrate, an LED light source attached to the substrate, an electrical connector attached to the substrate and electrically connected to the LED light source, a potting material on the substrate and covering at least a portion of the electrical connector; and a barrier separating the potting material from the LED light source, the barrier having a height that exceeds the thickness of the potting material on the substrate.

Abstract: A housing for an optoelectronic component is disclosed, having a plastic base body that has a front side with an assembly region for at least one radiation emitting or radiation detecting body, wherein the plastic base body is formed from at least one first plastic component and at least one second plastic component. The second plastic component is disposed on the front side of the plastic base body, and is formed from a material that differs from the first plastic component in at least one optical property, and forms an optically functional region of the plastic base body. Further, a method for producing a housing for an optoelectronic component and a light emitting diode component is disclosed.

Abstract: An LED leadframe package with surface tension function to enable the production of LED package with convex lens shape by using dispensing method is disclosed. The LED leadframe package of the invention is a PPA supported package house for LED packaging with metal base, four identical metal electrodes, and PPA plastic to fix the metal electrodes and the heat dissipation base together, four ring-alike structures with a sharp edge and with a tilted inner surface, and three ring-alike grooves formed between sharp edge ring-alike structures.

Abstract: A thin film transistor array panel is provided according to one or more embodiments. In an embodiment, the thin film transistor array panel includes: a base substrate that has a display area and a peripheral area; a plurality of thin film transistors that are formed in the display area; a plurality of signal input pads that are formed in the peripheral area and that are formed long in a first direction; and a plurality of signal lines that are connected to the thin film transistors and the signal input pads, wherein at least a part of each of the plurality of signal input pads is arranged in a line along the first direction.

Abstract: A semiconductor device includes a thyristor in which a first-conductivity-type first region, a second-conductivity-type second region having a conductivity type reverse to the first conductivity type, a first-conductivity-type third region, and a second-conductivity-type fourth region are sequentially arranged to form junctions. The third region is formed on a semiconductor substrate separated by an element isolation region. A gate electrode formed via a gate insulating film and side wall formed at wall side of both side of the gate electrode are provided on the third region, and the fourth region is formed so that one end thereof covers the joint portion between the other end of the third region and the element isolation regions, and so that the other end of the fourth region is joined with the sidewall on the other side.

Abstract: A group III nitride semiconductor light emitting device with a double sided electrode structure which has a low driving voltage as well as excellent light emission efficiency is provided, and the group III nitride semiconductor light emitting device includes at least an impurity layer 30 composed of a high concentration layer 3b made of a group III nitride semiconductor containing high concentration of impurity atoms, and a low concentration layer 3a made of a group III nitride semiconductor containing impurity atoms whose concentration is lower than that of the high concentration layer 3b; and a group III nitride semiconductor layer 2, and the lower concentration layer 3a and the high concentration layer 3b are continuously formed on the group III nitride semiconductor layer 2 in this order to form the group III nitride semiconductor light emitting device.

Abstract: A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.