Patents Examined by Farun Lu
  • Patent number: 10381467
    Abstract: According to an embodiment of a semiconductor device, the device includes first and second trenches formed in a semiconductor body and an electrode disposed in each of the trenches. One of the electrodes is a gate electrode, and the other electrode is electrically disconnected from the gate electrode. The semiconductor device further includes a semiconductor mesa between the trenches. The semiconductor mesa includes a separation region and at least one of a source region and a body region located in the semiconductor mesa. A drift zone is provided below the at least one of the source region and the body region. In the separation region, at least one of (i) a capacitive coupling between the gate electrode and the semiconductor mesa and (ii) a conductivity of majority charge carriers of the drift zone is lower than outside of the separation region.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 13, 2019
    Assignee: Infineon Technologies AG
    Inventors: Roman Baburske, Matteo Dainese, Peter Lechner, Hans-Joachim Schulze, Johannes Georg Laven
  • Patent number: 10381354
    Abstract: One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: August 13, 2019
    Assignee: GLOBALFOUNDARIES Inc.
    Inventors: Daniel Chanemougame, Emilie Bourjot
  • Patent number: 10381441
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, and a first insulating film. The first electrode includes a first conductive region. The second electrode includes a second conductive region. The first semiconductor region includes first to fourth partial regions. The second semiconductor region includes a fifth partial region. The third semiconductor region includes a sixth partial region provided between the fourth partial region and the fifth partial region. The fourth semiconductor region includes is electrically connected to the second conductive region, and includes first and second portions. The first insulating film includes first to third insulating regions. The first insulating region is positioned between the first portion and the first conductive region. The second insulating region contacts the fourth and sixth partial regions.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: August 13, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinya Kyogoku, Ryosuke Iljima
  • Patent number: 10373967
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: August 6, 2019
    Assignee: FLOADIA CORPORATION
    Inventors: Daisuke Okada, Kazumasa Yanagisawa, Fukuo Owada, Shoji Yoshida, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 10361153
    Abstract: Methods of forming vias include nitridizing exposed surfaces of a first layer and an exposed surface of a conductor underlying the first layer to form a layer of nitridation at said exposed surfaces. Material from the layer of nitridation at the exposed surface of the underlying conductor is etched away. The exposed surface of the underlying conductor is etched away to form a recessed area in the underlying conductor after etching away material from the layer of nitridation. A conductive via that forms a conductive contact with the underlying conductor is formed.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang
  • Patent number: 10355094
    Abstract: An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device. A conformal titanium liner is present on the sidewalls of the trench and is in direct contact with the at least one contact surface. The conformal titanium liner may be composed of 100 wt. % titanium, and may have a thickness ranging from 10 ? to 100 ?.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 10340172
    Abstract: This semiconductor wafer surface protection film has a substrate layer A, an adhesive absorption layer B, and adhesive surface layer C, in the stated order. The adhesive absorption layer B comprises an adhesive composition containing a thermoset resin b1, said adhesive absorption layer B having a minimum value G?bmin of the storage elastic modulus G?b in the range of 25° C. to less than 250° C. of 0.001 MPa to less than 0.1 MPa, a storage elastic modulus G?b250 at 250° C. of 0.005 MPa or above, and a temperature at which G?bmin is exhibited of 50-150° C. The adhesive surface layer C has a minimum value G?cmin of the storage elastic modulus G?c in the range of 25° C. to less than 250° C. of 0.03 MPa.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: July 2, 2019
    Assignee: MITSUI CHEMICALS TOHCELLO, INC.
    Inventors: Jun Kamada, Noboru Kawasaki, Shinichi Usugi, Makoto Sukegawa, Jin Kinoshita, Kouji Igarashi, Akimitsu Morimoto
  • Patent number: 10340341
    Abstract: A method of fabricating a semiconductor device includes forming a fin in a substrate and depositing a spacer material on the fin. The method includes recessing the spacer material so that a surface of the fin is exposed. The method includes removing a portion of the fin within lateral sidewalls of the spacer material to form a recess, leaving a portion of the fin on the lateral sidewalls. The method further includes depositing a semiconductor material within the recess.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin Kuo Chao, Kangguo Cheng, Nicolas Loubet
  • Patent number: 10332836
    Abstract: An integrated circuit structure includes a first low-k dielectric layer having a first k value, and a second low-k dielectric layer having a second k value lower than the first k value. The second low-k dielectric layer is overlying the first low-k dielectric layer. A dual damascene structure includes a via with a portion in the first low-k dielectric layer, and a metal line over and joined to the via. The metal line includes a portion in the second low-k dielectric layer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: June 25, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Chun Wang, Chung-Chi Ko, Po-Cheng Shih
  • Patent number: 10332911
    Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Shiqun Gu, Daeik Daniel Kim, Matthew Michael Nowak, Jonghae Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, David Francis Berdy
  • Patent number: 10325929
    Abstract: The present disclosure discloses a method for fabricating a display substrate, belonging to the technical field of displaying. The method includes: providing a base substrate having an array of Thin Film Transistors; forming a photoresist pattern on the base substrate, the photoresist pattern including a hollow region for forming a spacer pattern; forming a spacer material in the hollow region; and peeling the photoresist pattern so that the spacer material in the hollow region forms the spacer pattern.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: June 18, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Feng Zhang, Zhijun Lv, Wenqu Liu, Liwen Dong, Shizheng Zhang, Ning Dang, Zhiyong Liu
  • Patent number: 10326040
    Abstract: Embodiments relate to forming a conformable interface layers (clayers) on small semiconductor devices, such as light emitting diodes (LEDs) to facilitate adhesion with a pick-up head for operations during the manufacturing of an electronic display. A conformable material is formed in regions between LED dies on a carrier substrate and over the LED dies. A mask is applied over the conformable material to selectively cover the conformable material. Portions of the conformable material are exposed to light to selectively cure or not cure the portions of the conformable material. The conformable material between the LED dies is removed to form a conformable interface layer over each of the LED dies.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: June 18, 2019
    Assignee: Facebook Technologies, LLC
    Inventors: Oscar Torrents Abad, Tilman Zehender, Pooya Saketi, Karsten Moh
  • Patent number: 10326017
    Abstract: In an embodiment, this invention relates to a vertical field-effect transistor component including a bottom source-drain layer and a method of creating the same. The method of forming a bottom source-drain layer of a vertical field-effect transistor component can comprise forming an anchor structure on a substrate. A sacrificial layer can be deposited on a middle region of the substrate and a channel layer can be deposited on the sacrificial layer. A plurality of vertical fins can be formed on the substrate and the sacrificial layer can be removed such that the plurality of vertical fins in the middle region form a plurality of floating fins having a gap located between the plurality of floating fins and the substrate. The bottom source-drain layer can then be formed such that the bottom source-drain layer fills in the gap.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Shogo Mochizuki, Junli Wang
  • Patent number: 10325991
    Abstract: The present disclosure provides a transistor device. The transistor device includes an active region surrounded by an isolation structure, a gate structure disposed over the active region and the isolation structure, and a source/drain disposed in the active region. The gate structure includes a body portion extending in a first direction, a head portion extending in a second direction, and a pair of wing portions disposed at two opposite sides of the body portion. The first direction and the second direction are perpendicular to each other. Each of the wing portions is in contact with the head portion and the body portion.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: June 18, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shih-Ting Lin, Jhen-Yu Tsai
  • Patent number: 10325956
    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10319780
    Abstract: A light-emitting device includes a first semiconductor layer; a first, a second and a third light-emitting structures formed on the same first semiconductor layer; a first trench between the first and the second light-emitting structures; a second trench between the second and the third light-emitting structures, wherein the first and the second trenches include bottom portions exposing a surface of the first semiconductor layer; a third trench in one of the light-emitting structures, exposing the first semiconductor layer and extending along a direction parallel with the first semiconductor layer; an insulating bridge part in the first and the second trenches, connecting the light-emitting structures; a first electrode in the third trench, electrically connecting to the first semiconductor layer; and a second electrode, including a pad on one of the light-emitting structures and an extending part; wherein the extending part is formed on the insulating bridge part and extends to the light-emitting structures.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: June 11, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chen Ou, Chun-Wei Chang, Chih-Wei Wu, Sheng-Chih Wang, Hsin-Mei Tsai, Chia-Chen Tsai, Chuan-Cheng Chang
  • Patent number: 10319821
    Abstract: A silicon carbide substrate includes a carbon-surface-side principal surface and a silicon-surface-side principal surface. The silicon carbide substrate has a diameter of 100 mm or greater and a thickness of 300 ?m or greater. An off angle of the carbon-surface-side principal surface and the silicon-surface-side principal surface relative to a {0001} plane is smaller than or equal to 4°. A nitrogen concentration in the carbon-surface-side principal surface is higher than a nitrogen concentration in the silicon-surface-side principal surface, and a difference in Raman peak shift between the carbon-surface-side principal surface and the silicon-surface-side principal surface is smaller than or equal to 0.2 cm?1.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: June 11, 2019
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Shunsaku Ueta, Kyoko Okita, Shin Harada
  • Patent number: 10319653
    Abstract: A semiconductor apparatus includes a semiconductor device, on-semiconductor-device metal pad and metal interconnect each electrically connected to the semiconductor device, a through electrode and a solder bump each electrically connected to the metal interconnect, a first insulating layer on which the semiconductor device is placed, a second insulating layer formed on the semiconductor device, a third insulating layer formed on the second layer. The metal interconnect is electrically connected to the semiconductor device via the on-semiconductor-device metal pad at an upper surface of the second layer, penetrates the second layer from its upper surface, and is electrically connected to the through electrode at an lower surface of the second layer, and an under-semiconductor-device metal interconnect is between the first layer and the semiconductor device, and the under-semiconductor-device metal interconnect is electrically connected to the metal interconnect at the lower surface of the second layer.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: June 11, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Katsuya Takemura, Kyoko Soga, Satoshi Asai, Kazunori Kondo, Michihiro Sugo, Hideto Kato
  • Patent number: 10319864
    Abstract: A vertical memory device and a method of manufacturing such device are provided. The vertical memory device may include a plurality of gate electrode layers stacked in a cell region of a semiconductor substrate; a plurality of upper isolation insulating layers dividing an uppermost gate electrode layer among the plurality of gate electrode layers, extending in a first direction; a plurality of vertical holes arranged to have any two adjacent vertical holes to have a uniform distance from each other throughout the cell region and including a plurality of channel holes penetrating through the plurality of gate electrode layers disposed between the plurality of upper isolation insulating layers and a plurality of first support holes penetrating through the plurality of upper insulating layers; a plurality of channel structures disposed in the plurality of channel holes; and a plurality of first support structures disposed in the plurality of first support holes.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuk Kim, Dae Hyun Jang, Seung Pil Chung, Sung Il Cho
  • Patent number: 10319836
    Abstract: A vertical transistor structure is provided that includes a bottom source/drain structure that includes a doped semiconductor buffer layer that contains a first dopant species having a first diffusion rate, and an epitaxial doped semiconductor layer that contains a second dopant species that has a second diffusion rate that is less than the first diffusion rate. During a junction anneal, the first dopant species readily diffuses from the doped semiconductor buffer layer into a pillar portion of a base semiconductor substrate to provide the bottom source/drain extension and bottom source/drain junction. No diffusion overrun is observed. During the junction anneal, the second dopant species remains in the epitaxial doped semiconductor layer providing a low resistance contact. The second dopant species does not interfere with the bottom source/drain extension and bottom source/drain junction due to limited diffusion of the second dopant species.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Shogo Mochizuki