Abstract: A semiconductor device includes a source/drain pattern disposed on a substrate and a source/drain contact connected to the source/drain pattern. The source/drain contact includes a lower contact structure extending in a first direction and an upper contact structure protruding from the lower contact structure. The upper contact structure includes a first sidewall and a second sidewall facing away from each other in the first direction. The first sidewall of the upper contact structure includes a plurality of first sub-sidewalls, and each of the first sub-sidewalls includes a concave surface.

Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.

Abstract: A display apparatus including a heteromorphy lens disposed on a path of light emitted from a light-emitting device, a side surface of the heteromorphy lens toward a first direction has a shape different from a side surface of the heteromorphy lens toward a second direction perpendicular to the first direction, so that light can be condensed in the first direction and diffused in the second direction due to the heteromorphy lens, and the reduction in luminance can be minimized, and the viewing angle can be limited.

Abstract: Methods for forming microelectronic devices include forming a staircase structure in a stack structure having a vertically alternating sequence of insulative and conductive materials arranged in tiers. Steps are at lateral ends of the tiers. Contact openings of different aspect ratios are formed in fill material adjacent the staircase structure, with some openings terminating in the fill material and others exposing portions of the conductive material of upper tiers of the stack structure. Additional conductive material is selectively formed on the exposed portions of the conductive material. The contact openings initially terminating in the fill material are extended to expose portions of the conductive material of lower elevations. Contacts are formed, with some extending to the additional conductive material and others extending to conductive material of the tiers of the lower elevations. Microelectronic devices and systems incorporating such staircase structures and contacts are also disclosed.

Abstract: A display substrate, a manufacturing method thereof and a display apparatus are disclosed. The display substrate includes a silicon base substrate and a color film layer disposed on the silicon base substrate. A plurality of metal traces for connecting a display area and a cathode ring with a bonding area respectively are contained in the silicon base substrate. The color film layer includes a first align mark, and the first align mark has a hollowed-out structure. A projection of the first align mark on the silicon base substrate and projections of the metal traces on the silicon base substrate include overlapping areas.

Abstract: In certain examples, methods and semiconductor structures are directed to an integrated circuit (IC) having a diamond layer section and a GaN-based substrate being monolithically integrated or bonded as part of the same IC. In a specific example, the GaN-based substrate includes GaN, AlxGayN (0<x<1; x+y=1) and a dielectric layer, and a diamond layer section which may include polycrystalline diamond. The IC includes: a GaN-based field effect transistor (FET) integrated with a portion of the GaN-based substrate, and a diamond-based FET integrated with a portion of the diamond layer section, the diamond FET being electrically coupled to the GaN-based FET and situated over or against a surface region of the GaN-based substrate.

Abstract: A semiconductor structure includes a substrate including a base and a plurality of fins discretely formed over the base. Each fin is made of a material including a first atom and contains openings therein. The semiconductor structure also includes a source-drain doped layer located in each opening and including a seed layer on a surface of an inner wall of the opening and a body layer on a surface of the seed layer. A material of the seed layer includes the first atom, a second atom, and a third atom. A material of the body layer includes the first atom and the second atom.

Abstract: A semiconductor device includes a channel component of a transistor and a gate component disposed over the channel component. The gate component includes: a dielectric layer, a first work function metal layer disposed over the dielectric layer, a fill-metal layer disposed over the first work function metal layer, and a second work function metal layer disposed over the fill-metal layer.

Abstract: A semiconductor device includes a substrate including traces, wherein the traces protrude above a top surface of the substrate; a prefill material over the substrate and between the traces; a die attached over the substrate; and a wafer-level underfill between the prefill material and the die.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a pillar, a strip part, a plurality of first contacts, and a second contact. The stacked body includes a plurality of conductive layers stacked via an insulating layer, and includes, at each of opposite ends in a first direction, a first staircase part in which the conductive layers are terminated stepwise. The pillar extends in the stacked body in a stacking direction of the stacked body, and form memory cells at positions intersecting with at least some conductive layers of the plurality of conductive layers. The strip part divides the stacked body in the first direction by extending in a second direction crossing the first direction. The plurality of first contacts are arranged in the first staircase part, in which each of the first contacts is connected to one of the conductive layers at each step of the first staircase part.

Abstract: A display panel includes: a substrate, a display area and a notch area on the substrate, and a capacitance compensation area. The display area at least partially surrounds the notch area, and the capacitance compensation area is located on a side of the display area facing the notch area. The capacitance compensation area includes a plurality of capacitance compensation units, and each capacitance compensation unit of at least some of the plurality of capacitance compensation units includes: a first conductive layer, a second conductive layer, and a first insulating layer between the first conductive layer and the second conductive layer. The first conductive layer is electrically connected to one of a plurality of gate lines, and an orthographic projection of the second conductive layer on the substrate at least partially overlaps with an orthographic projection of the first conductive layer on the substrate.

Abstract: A transistor structure is disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a second gate structure on the thicker portion of the dielectric layer. The transistor may include a third gate structure on the thicker portion.

Abstract: A semiconductor device such as a fin field effect transistor and its method of manufacture are provided. In some embodiments gate spacers are formed over a semiconductor fin, and a first gate stack is formed over the fin. A first sacrificial material with a large selectivity to the gate spacers is formed over the gate stack, and a second sacrificial material with a large selectivity is formed over a source/drain contact plug. Etching processes are utilized to form openings through the first sacrificial material and through the second sacrificial material, and the openings are filled with a conductive material.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first transistor, a first resistive random access memory (RRAM) resistor, and a second RRAM resistor. The first resistor includes a first resistive material layer, a first electrode shared by the second resistor, and a second electrode. The second resistor includes the first electrode, a second resistive material layer, and a third electrode. The first electrode is electrically coupled to the first transistor.

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.

Abstract: A light-emitting device and a display device using the same are disclosed. The light-emitting device improves the reliability of a process of disposing light-emitting devices. The light-emitting device is configured to ensure electrical connections even if the light-emitting device is inverted while being disposed on a substrate. The light-emitting device includes an n-type semiconductor layer and a p-type semiconductor layer. N-type electrodes and p-type electrodes are disposed on both sides of top and bottom surfaces of the light-emitting device. Contact holes are provided to electrically connect one of the n-type electrodes to the n-type semiconductor layer and one of the p-type electrodes to the p-type semiconductor layer. When the light-emitting device is inverted while being disposed on a substrate, the light-emitting device operates ordinarily, thereby reducing the defect rate of a display device.

Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.

Abstract: A semiconductor device includes a first and second active pattern extending in a first direction on a substrate, a first and second gate electrode extending in a second direction to intersect the first and second active pattern, a first source/drain contact extending in the second direction and connected to a first and source/drain region of the first and second active patterns, respectively, a first source/drain via connected to the first source/drain contact, a first cell separation film extending in the second direction and crosses the first active pattern and the second active pattern, between the first source/drain contact and the second gate electrode, a first gate via connected to the second gate electrode and arranged with the first source/drain via along the first direction, and a first connection wiring which extending in the first direction and connects the first source/drain via and the first gate via.

Abstract: An electrostatic discharge (ESD) protection device includes a pad, a diode, a gate ground NMOS (GGNMOS) transistor and a thyristor. The diode includes an anode connected with the pad. The GGNMOS transistor is connected between a cathode of the diode and a ground terminal. The thyristor is formed between the diode and the ground terminal when an ESD current may flow from the pad.