Patents Examined by Farun Lu
  • Patent number: 11037881
    Abstract: A component carrier includes a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, a first component embedded in the stack, having at least one first pad on a bottom surface of the first component. The at least one first pad is electrically connected with a bottom surface of the stack. A second component embedded in the stack, having at least one second pad on a top surface of the second component. The at least one second pad is electrically connected with a top surface of the stack. The stack includes a first redistribution structure electrically connecting the at least one first pad of the first component with the bottom surface of the stack, and a second redistribution structure electrically connecting the at least one second pad of the second component with the top surface of the stack.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: June 15, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventor: Markus Leitgeb
  • Patent number: 11031460
    Abstract: An integrated circuit device includes a conductive region on a substrate and a lower electrode structure including a main electrode part spaced apart from the conductive region and a bridge electrode part between the main electrode part and the conductive region. A dielectric layer contacts an outer sidewall of the main electrode part. To manufacture the integrated circuit device, a preliminary bridge electrode layer is formed in a hole of a mold pattern on the substrate, and the main electrode part is formed on the preliminary bridge electrode layer in the hole. The mold pattern is removed to expose a sidewall of the preliminary bridge electrode layer, and a portion of the preliminary electrode part is removed to form the bridge electrode part. The dielectric layer is formed to contact the outer sidewall of the main electrode part.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-goo Kang, Hyun-suk Lee, Gi-hee Cho
  • Patent number: 11018127
    Abstract: A SGT MOSFET having ESD diode and a method of manufacturing the same are disclosed. The SGT trench MOSFET according to the present invention, has n+ doped shielded electrode in an N channel device and requires only two poly-silicon layers, making the device can be shrunk with reducing shielded gate width for Rds reduction without increasing switching loss and having dynamic switching instability.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 25, 2021
    Assignee: NAMI MOS CO, LTD.
    Inventor: Fu-Yuan Hsieh
  • Patent number: 11011530
    Abstract: When a memory cell (MC) is downsized by reducing the distance between a drain region (12a) and a source region (12b) on the surface of a fin (S2) with a high impurity concentration inside the fin (S2), the shape of the fin (S2) can be set such that a potential difference between a memory gate electrode (MG) and the fin (S2) is reduced to suppress the occurrence of disturbance. Accordingly, the memory cell (MC) achieves downsizing and suppression of the occurrence of disturbance.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: May 18, 2021
    Assignee: FLOADIA CORPORATION
    Inventors: Daisuke Okada, Kazumasa Yanagisawa, Fukuo Owada, Shoji Yoshida, Yasuhiko Kawashima, Shinji Yoshida, Yasuhiro Taniguchi, Kosuke Okuyama
  • Patent number: 11011606
    Abstract: A silicon carbide substrate has a trench extending from a main surface of the silicon carbide substrate into the silicon carbide substrate. The trench has a trench width at a trench bottom. A shielding region is formed in the silicon carbide substrate. The shielding region extends along the trench bottom. In at least one doping plane extending approximately parallel to the trench bottom, a dopant concentration in the shielding region over a lateral first width deviates by not more than 10% from a maximum value of the dopant concentration. The first width is less than the trench width and is at least 30% of the trench width.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 18, 2021
    Assignee: Infineon Technologies AG
    Inventors: Andreas Meiser, Caspar Leendertz, Anton Mauder
  • Patent number: 11011468
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a target layer, a plurality of metal pads, a plurality of conductive lines, a plurality of conductive plugs, an isolating liner, and a plurality of metal contacts. The semiconductor substrate has a front surface, a rear surface opposite to the front surface, and an implanted region connected to the rear surface. The target layer is disposed over the front surface. The metal pads are disposed over the target layer. The plurality of conductive lines are disposed within the semiconductor substrate and the target layer and connected to the metal pads. The conductive plugs are disposed in the implanted region. The isolating liner encircles the conductive plugs. The metal contacts are disposed over the conductive lines and the conductive plugs.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: May 18, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Hsih-Yang Chiu
  • Patent number: 11004798
    Abstract: Embodiments of the disclosure are drawn to arrangements of one or more “cuts” or pattern of cuts in conductive structures. Wiring layers may each include a cut pattern including a set of cuts through conductive structures of the wiring layers where each of the cuts is offset from the other in a direction orthogonal to the cut. The cut pattern in a wiring layer may be orthogonal to the cut pattern in another wiring layer. In some examples, the cut pattern may be a stair-step pattern. In some examples, the cut pattern may be interrupted by other conductive structures.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: May 11, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hirokazu Matsumoto, Ryota Suzuki, Mitsuki Koda, Makoto Sato
  • Patent number: 10998400
    Abstract: A semiconductor device includes a semiconductor layer having first and second planes; a first semiconductor region of a first conductivity type; second and third semiconductor regions of a second conductivity type between the first semiconductor region and the first plane; a fourth semiconductor region of a first conductivity type between the second semiconductor region and the first plane; a fifth semiconductor region of a first conductivity type between the third semiconductor region and the first plane; first and second trenches between the fourth and fifth semiconductor regions and over from the second to third semiconductor region; a sixth semiconductor region between the second and third semiconductor regions and between the first and second trenches; a seventh semiconductor region of a second conductivity type between the first trench and the first semiconductor region and contacting the second and third semiconductor regions; a first and second gate electrode in the trenches.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: May 4, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tatsuo Shimizu
  • Patent number: 10991646
    Abstract: A flexible circuit board for a display, having a chip-on-film structure, is disclosed. A connection pattern which is selected as a first connection pattern among connection patterns connected to panel contact pads does not reach a cutting line and is confined within a product region. As a consequence, the connection pattern selected as the first connection pattern may be prevented from being exposed on a cutting section along the cutting line, and thus, may be prevented from being changed in its electrical property due to penetration of moisture.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: April 27, 2021
    Assignee: Silicon Works Co., Ltd.
    Inventors: Kyung Jik Min, Ju Young Shin, Ji Hyun Hwang, Jung Bae Yun
  • Patent number: 10985224
    Abstract: Provided is a display panel having a display area including a first display area and a second display area. The display panel includes: a substrate; an array layer; a display layer including light-emitting elements each including an anode, a light-emitting layer and a cathode that are sequentially stacked; the light-emitting elements comprises first light-emitting elements and second light-emitting elements; a state switching layer located at a side of the display layer facing away from a display surface of the display panel and located in the first display area, wherein in a direction perpendicular to the display panel, the state switching layer overlaps the first light-emitting elements; the state switching layer is switchable between a first state and a second state, and the state switching layer has a smaller light transmittance in the first state than in the second state; and an optical element.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: April 20, 2021
    Assignee: Shanghai Tianma AM-OLED Co., Ltd.
    Inventors: Yuhao Liu, Mingzhi Dai, Jinghua Niu
  • Patent number: 10980106
    Abstract: Apparatus related to conformal coating implemented with surface mount devices. In some embodiments, a radio-frequency (RF) module includes a packaging substrate configured to receive a plurality of components. The RF also includes a surface mount device (SMD) mounted on the packaging substrate, the SMD including a metal layer that faces upward when mounted. The RF module further includes an overmold formed over the packaging substrate, the overmold dimensioned to cover the SMD. The RF module further includes an opening defined by the overmold at a region over the SMD, the opening having a depth sufficient to expose at least a portion of the metal layer. The RF module further includes a conformal conductive layer formed over the overmold, the conformal conductive layer configured to fill at least a portion of the opening to provide an electrical path between the conformal conductive layer and the metal layer of the SMD.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: April 13, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Anthony James Lobianco, Howard E. Chen, Robert Francis Darveaux, Hoang Mong Nguyen, Matthew Sean Read, Lori Ann Deorio
  • Patent number: 10971578
    Abstract: The disclosure concerns a capacitive component including a trench and, vertically in line with the trench, first portions of a first silicon oxide layer and first portions of second and third conductive layers including polysilicon or amorphous silicon, the first portion of the first layer being between and in contact with the first portions of the second and third layers.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: April 6, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Abderrezak Marzaki, Pascal Fornara
  • Patent number: 10971594
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Patent number: 10971631
    Abstract: The present application provides a thin film transistor (TFT) and a method of fabricating the same, a display substrate and a method of fabricating the same, and a display device. The TFT includes a substrate, and a source electrode, a drain electrode and an active layer on the substrate. The active layer includes first and second active layers, the first active layer has a carrier mobility greater than that of the second active layer, and the second active layer is closer to the source electrode and the drain electrode than the first active layer. An orthographic projection of the source electrode on the substrate and an orthographic projection of the drain electrode on the substrate at least partially overlap with an orthographic projection of the second active layer on the substrate, respectively, and the first active layer is separated from the source electrode and the drain electrode.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 6, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Binbin Cao
  • Patent number: 10966322
    Abstract: A semiconductor device includes: a sealed unit that seals a semiconductor element therein; a connection terminal that is electrically connected to the semiconductor element and is provided so as to project outward from the sealed unit; and a pedestal that is provided to surround a bottom part of an exposed portion of the connection terminal that is exposed from the sealed unit. The pedestal has a base attached to the sealed unit and a guide part that has an inclined side face.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano
  • Patent number: 10964746
    Abstract: Some embodiments of the present disclosure relate to a method in which a functional layer is formed over an upper semiconductor surface of a semiconductor substrate, and a capping layer is formed over the functional layer. A first etchant is used to form a recess through the capping layer and through the functional layer. The recess has a first depth and exposes a portion of the semiconductor substrate there through. A protective layer is formed along a lower surface and inner sidewalls of the recess. A second etchant is used to remove the protective layer from the lower surface of the recess and to extend the recess below the upper semiconductor surface to a second depth to form a deep trench. To prevent etching of the functional layer, the protective layer remains in place along the inner sidewalls of the recess while the second etchant is used.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Hsien Chou, Shih Pei Chou, Chih-Yu Lai, Sheng-Chau Chen, Chih-Ta Chen, Yeur-Luen Tu, Chia-Shiung Tsai
  • Patent number: 10957590
    Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: March 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Wenhui Wang, Huixiong Dai, Christopher S. Ngai, Liqi Wu, Wenyu Zhang, Yongmei Chen, Hao Chen, Keith Tatseun Wong, Ke Chang
  • Patent number: 10957638
    Abstract: A device with pillar-shaped components, includes a substrate; a wiring layer disposed on the substrate; and pillar-shaped components disposed on any of the substrate and the wiring layer, each of the pillar-shaped components having a bottom part connected to the substrate and/or the wiring layer, a top part opposed to the bottom part, and a lateral face part extending from the bottom part and connected to the top part; wherein each of the pillar-shaped components includes a first pillar-shaped part formed by plating, a second pillar-shaped part formed on the first pillar-shaped part by plating, and a ring-like projection part formed on the lateral face part to project outward and extend in a circumferential direction, and to be in a position higher than a joint position between the first pillar-shaped part and the second pillar-shaped part.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: March 23, 2021
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Osamu Koike
  • Patent number: 10957550
    Abstract: A semiconductor structure and a formation method thereof are provided. The formation method includes: providing a base, the base including a pattern dense region and a pattern isolated region; forming a plurality of separate hard mask layers on the base, where adjacent hard mask layers and the base define an opening, and an opening of the pattern isolated region is wider than an opening of the pattern dense region; forming a trimming layer at least on a side wall of the opening of the pattern isolated region, the trimming layer and the hard mask layer constituting a mask structure layer; and etching, using the mask structure layer as a mask, a portion of the thickness of the base exposed by the opening to form a plurality of target pattern layers protruding from the remaining base. Embodiments and implementations of the present disclosure are advantageous for improving a critical dimension uniformity of a target pattern layer in each region.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: March 23, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semconductor Manufacturing (Shanghai) International Corporation
    Inventors: Haiyang Zhang, Erhu Zheng
  • Patent number: 10954593
    Abstract: There is provided a tungsten film-forming method, including: forming a silicon film on a substrate in a reduced pressure atmosphere by disposing the substrate having a protective film formed on a surface of the substrate in a processing container; forming an initial tungsten film by supplying a tungsten chloride gas to the substrate having the silicon film formed thereon; and forming a main tungsten film by supplying a tungsten-containing gas to the substrate having the initial tungsten film formed thereon.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 23, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Takashi Sameshima, Koji Maekawa, Katsumasa Yamaguchi