Abstract: A capacitor structure comprises a first conductive region having a first conductivity type and a second conductive region having a second conductivity type different than the first conductivity type. The first conductive region comprises a first protrusion portion and a second protrusion portion. The second conductive region comprises a protrusion portion. The capacitor structure further comprises a first dielectric overlying the first protrusion portion of the first conductive region, and a first conductor overlying the first dielectric. Additionally, the capacitor structure comprises a terminal of a diode overlying the second protrusion portion of the first conductive region and the protrusion portion of the second conductive region. The terminal of the diode comprises a second conductor isolated from the first conductor.

Abstract: A method for manufacturing a light-emitting device includes: providing an intermediate body having a first ultraviolet transmitting layer, a first adhesive layer, a plurality of first light emitting elements, a second adhesive layer, and a second ultraviolet transmitting layer; disposing on the second ultraviolet transmitting layer of the intermediate body, an ultraviolet shielding layer in a region corresponding to a part of the first light-emitting elements; performing first ultraviolet irradiation of irradiating the intermediate body with ultraviolet from a direction facing the ultraviolet shielding layer; performing second ultraviolet irradiation of irradiating the intermediate body with ultraviolet from a direction facing the first ultraviolet transmitting layer; and separating the part of the first light-emitting elements from the first adhesive layer along with the second adhesive layer.

Abstract: Described examples include a method having steps of forming an isolation pad oxide layer on a substrate and forming and patterning a silicon nitride layer on the isolation pad oxide layer. The method also has steps of oxidizing portions of the substrate not covered by the silicon nitride layer to form a LOCOS layer and oxidizing the silicon nitride layer in an oxidizing ambient containing a chlorine source to form a silicon dioxide layer.

Abstract: An ovonic threshold switch (OTS) selector and a memory device including the OTS selector is provided. The OTS selector includes a switching layer formed of a GeCTe compound further doped with one or both of nitrogen and silicon, and exhibits improved thermal stability and electrical performance.

Abstract: There is provided a technique that includes forming a film in a concave portion provided on a surface of a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a precursor to the substrate; (b) supplying a nitrogen-containing reactant to the substrate; and (c) supplying an oxygen-containing reactant to the substrate, wherein in (c), an oxide layer is formed by oxidizing a layer, which has been formed in the concave portion before (c) is performed, and an amount of oxidation of the oxide layer formed in an upper portion in the concave portion is made larger than an amount of oxidation of the oxide layer formed in a lower portion in the concave portion.

Abstract: An IC structure includes an MFMIS memory cell on a semiconductor substrate, and a CMOS transistor adjacent the MFMIS memory cell on the same semiconductor substrate. A method provides co-integration of the MFMIS memory cell with the CMOS transistor. The method may optionally co-integrate an MFIS memory cell. The IC structure and method provide a lower cost approach to forming MFMIS memory cells, which provide a number of advantages over MFIS memory cells.

Abstract: In an LED display device according to an embodiment of the present disclosure, the LED display device comprises a second pixel driving circuit on a substrate, an LED element attached to a region not overlapping the second pixel driving circuit, including a first LED element, a second LED element and a growth substrate, and providing a double light-emitting spectrum, an element fixing layer surrounding the LED element, a first pixel driving circuit on the element fixing layer, and an element protecting layer on the first pixel driving circuit. In addition, the first LED element is controlled by the first pixel driving circuit, and the second LED element is controlled by the second pixel driving circuit. Therefore, the LED display device provides a dual emission spectrum, can realized high luminance and high definition, and can prevent a pixel defect.

Abstract: A method of processing a substrate that includes: forming a first plurality of lines and a first plurality of recesses, each of the plurality of lines being separated from an adjacent one of the plurality of lines by one of the plurality of recesses, the first plurality of lines including a first material and formed over a to-be-patterned layer; performing a cyclic process including: depositing a mask material over the first plurality of lines and within the first plurality of recesses, the mask material deposited defining a second plurality of lines, each of the second plurality of lines dividing one of the first plurality of recesses to form a second plurality of recesses; and performing a trimming process to increase critical dimensions of the second plurality of recesses; and patterning the to-be-patterned layer using the first plurality of lines and the second plurality of lines as an etch mask.

Abstract: A light-emitting device includes a substrate provided with a first wiring and a second wiring, a first element including a first electrode pad, a second element including a second electrode pad, a first wire connecting the second wiring and the first electrode pad and including a first wire horizontal part that is level with respect to a top surface of the first element, a second wire connecting the second wiring and the second electrode pad and including a second wire horizontal part that is level with respect to the top surface of the first element, and a reflective resin exposing the top surface of the first element. The reflective resin has a bulged portion in a bulged dike shape such that a surface of the reflective resin is brought into contact with at least a part of the second wire horizontal part and extends along the second wire horizontal part.

Abstract: Disclosed are a leadframe, a bracket and an LED device. The leadframe includes a first photo-etched metal part, having a first electrode and a chip placement layer thereon, which has a greater length for short and long edges than those of the first electrode; and a second photo-etched metal part, composed of a second electrode and a connection layer thereon, which has a greater length for short and long edges than those of the second electrode; wherein a first long edge of the chip placement layer is flush with a first long edge of the first electrode, and a first long edge of the connection layer is flush with a first long edge of the second electrode; and wherein the chip placement layer and the connection layer are provided with L-shaped pins at corners of their first long edges to cover sidewalls of the corresponding corners.

Abstract: A bezel-less display panel, a display device, and a spliced display device are disclosed. The bezel-less display panel includes a first display area, a second display area around the first display area, and a third display area around the second display area. The third display area is not provided with a subpixel driving thin-film transistor. Some of driving thin-film transistors in the second display area are connected to light-emitting subpixels in the third display area through a plurality of metal lines.

Abstract: A light emitting device is a micro-scale light emitting device including a semiconductor stack, an insulation layer, and a metal reflection layer. The semiconductor stack includes a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer disposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. The insulation layer covers upper and side surfaces of the semiconductor stack. The metal reflection layer is disposed on the insulation layer, and covers at least a portion of the side surface of the semiconductor stack. The insulation layer includes a distributed Bragg reflector.

Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

Abstract: Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the SSL structure. The first or second contact is configured to provide a current density profile in the SSL structure based on a target current density profile.

Abstract: A chip package structure is provided. The chip package structure includes a first substrate. The chip package structure includes a conductive via structure passing through the first substrate. The chip package structure includes a barrier layer over a surface of the first substrate. The chip package structure includes an insulating layer over the barrier layer. The chip package structure includes a conductive pad over the insulating layer. The conductive pad has a first portion passing through the insulating layer and the barrier layer and connected to the conductive via structure. The chip package structure includes a conductive bump over the conductive pad. The chip package structure includes a second substrate. The chip package structure includes an underfill layer between the first substrate and the second substrate.

Abstract: A magnetoresistive sensor and a manufacturing method thereof are provided. The method includes: forming an initial reference layer in an annular shape, wherein the initial reference layer includes an anti-ferromagnetic layer and a ferromagnetic layer; performing a heat treatment on the initial reference layer, wherein the ferromagnetic layer is magnetized to have a magnetization direction oriented along a vortex path during a heating step of the heat treatment, and an exchange bias oriented along the vortex path is induced at an interface of the anti-ferromagnetic layer and the ferromagnetic layer during a cooling step of the heat treatment; patterning the initial reference layer to form separated reference layers, wherein the reference layers are respectively formed in a annular sector shape, and the reference layers are arranged along the vortex path; forming spacer layers and free layers to form magnetoresistive devices; routing the magnetoresistive devices to form the magnetoresistive sensor.

Abstract: A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.

Abstract: Examples of an integrated circuit with a capacitor structure and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate and a trench isolation material disposed on the substrate. An isolation structure is disposed on the trench isolation material. A first electrode disposed on the isolation structure, and a second electrode disposed on the isolation structure. A capacitor dielectric is disposed on the isolation structure between the first electrode and the second electrode. In some such examples, the isolation structure includes a first hard mask disposed on the trench isolation material, a dielectric disposed on the first hard mask, and a second hard mask disposed on the dielectric.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer, at least one part of the light emitting layer being formed between adjacent micro-LEDs. the micro-LED chip further comprises a metal layer formed on the light emitting layer between the adjacent micro-LEDs.

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.