Patents Examined by Feifei Yeung-Lopez
  • Patent number: 10446620
    Abstract: An organic light-emitting diode display device is disclosed. The organic light-emitting diode display device comprises a display panel where a plurality of pixels are arranged. The plurality of pixels comprise a first pixel having a first planar shape consisting of a plurality of points and a second pixel placed adjacent to the first pixel and having a second planar shape consisting of a plurality of points. The first planar shape contains a first point, which is the only point from which the shortest distance between the first pixel and the second pixel is obtained.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: October 15, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Changhwa Jun, Howon Choi
  • Patent number: 10446515
    Abstract: A semiconductor substrate includes a first dielectric layer, a first patterned conductive layer disposed in the first dielectric layer, a second dielectric layer disposed on the first dielectric layer, and a first bump pad disposed in the second dielectric layer. The first bump pad is electrically connected to the first patterned conductive layer, and the first bump pad has a curved surface surrounded by the second dielectric layer.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: October 15, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li Chuan Tsai, Chih-Cheng Lee
  • Patent number: 10446447
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a liner on the fin-shaped structure; and removing the liner and part of the fin-shaped structure so that a sidewall of the fin-shaped structure comprises a curve. Moreover, the method includes forming an epitaxial layer around the sidewall of the fin-shaped structure while a top surface of the fin-shaped structure is exposed.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: October 15, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-Fan Li, I-Cheng Hu, Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin, Chun-Yuan Wu
  • Patent number: 10438932
    Abstract: A semiconductor device has an interposer including a plurality of conductive vias formed through the interposer. A first semiconductor die is disposed over the interposer. A second semiconductor die is disposed over a first substrate. The first semiconductor die and second semiconductor die are power semiconductor devices. The interposer is disposed over the second semiconductor die opposite the first substrate. A second substrate is disposed over the first semiconductor die opposite the interposer. The first substrate and second substrate provide heat dissipation from the first semiconductor die and second semiconductor die from opposite sides of the semiconductor device. A plurality of first and second interconnect pads is formed in a pattern over the first semiconductor die and second semiconductor die. The second interconnect pads have a different area than the first interconnect pads to aid with alignment when stacking the assembly.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: October 8, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jinchang Zhou, Yusheng Lin, Mingjiao Liu
  • Patent number: 10424653
    Abstract: A method for fabricating a semiconductor structure includes the following steps. A plurality of dielectric layers is formed on a substrate, wherein the material composition and layer positioning of each of the plurality of dielectric layers are selected to enable defined junctions for one or more features of the semiconductor structure. A trench is formed through each of the plurality of dielectric layers to the top of the substrate, wherein the height and width dimensions of the trench are selected in accordance with an aspect ratio trapping process. A vertical fin structure is formed by epitaxially growing material within the trench on the top of the substrate. In further steps, gate stack and source/drain regions are formed around the vertical fin structure in accordance with the positioning of the plurality of dielectric layers. The resulting semiconductor structure, in one or more examples, is a vertical transport field-effect transistor.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chen Zhang, Kangguo Cheng, Xin Miao, Wenyu Xu
  • Patent number: 10424622
    Abstract: A display device comprised of OLEDs and micro LEDs which allows for blue light degradation of the OLEDs includes a first substrate and a second substrate in a double-decked configuration. First light emitting elements are located and spaced on the first substrate and second light emitting elements are located and spaced on the second substrate, the light emitting elements on the lower deck being staggered so as not to be hidden by the light emitting elements on the upper deck. The upper deck has openings (or is transparent) therein to allow egress of light from the light emitting elements of the lower deck. The display device provides a solution for uneven display cause by degradation of pixels.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: September 24, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chang-Ting Lin, Wei-Chih Chang, Ying-Chieh Chen, Chung-Wen Lai, Chun-Chieh Huang, Wei-Li Wang, Po-Yi Lu, Jen-Jie Chen, I-Wei Wu
  • Patent number: 10416490
    Abstract: A curved display comprises a first substrate 100 and a second substrate 200 that are disposed opposite to each other and both curved along the first direction. The first substrate includes data lines 11 and gate lines 12. The second substrate includes light transmission parts 202 and a light shielding part 203. The light shielding part includes first light shielding portions 203b extending in the first direction and second light shielding portions 203a extending in a second direction. The second light shielding portions include a central light shielding portion a5, a first end light shielding portion al disposed on one end side in the first direction, and a middle light shielding portion disposed therebetween. A width in the first direction of the middle light shielding portion is greater than or equal to that of the central light shielding portion and the first end light shielding portion.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: September 17, 2019
    Assignee: Panasonic Liquid Crystal Display Co., Ltd.
    Inventors: Masafumi Hirata, Hiroaki Goto, Takeshi Aramaki, Masashi Kuno
  • Patent number: 10410959
    Abstract: Package deflection and mechanical stress of microelectronic packaging is minimized in a two step manufacturing process. In a first step, a ceramic insulator is high-temperature bonded between a wraparound lead layer and a buffer layer of a same material as the lead layer to provide a symmetrically balanced three-layer structure. In a second step, the three-layer structure is high temperature bonded, using a lower melt point braze, to a heat spreader. This package configuration minimizes package deflection, and thereby improves thermal dissipation and reliability of the package.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 10, 2019
    Assignee: Kyocera International, Inc.
    Inventors: Franklin Kim, Mark Eblen, Shinichi Hira
  • Patent number: 10403522
    Abstract: A heater or cooler chamber for a batch of more than one workpiece includes a heat storage block. In the block a multitude of pockets are provided, whereby each of the pockets may be closed or opened by a controllably operated door. A heater or cooler arrangement is applied. The pockets are tailored to surround a workpiece applied therein in a non-contact closely spaced manner.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: September 3, 2019
    Assignee: EVATEC AG
    Inventor: Jurgen Weichart
  • Patent number: 10396169
    Abstract: Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on a substrate. A second nanosheet stack having a first sacrificial layer between a first nanosheet and a second nanosheet is formed on the substrate. The first nanosheet of the first nanosheet stack is doped and concurrently removed with the first sacrificial layer of the first nanosheet stack and the first sacrificial layer of the second nanosheet stack.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10395942
    Abstract: During a first period, pure water used as a low-volatile liquid is supplied onto a substrate while the substrate is rotated. After discharge of the low-volatile liquid is stopped, the low-volatile liquid remains in a large region on a DSA film. The low-volatile liquid is held on the DSA film without reacting with the DSA film. During a subsequent second period, an organic solvent is supplied to the substrate while the substrate is rotated. The organic solvent supplied to the substrate is mixed with the low-volatile liquid remaining on the DSA film. In this case, volatilization of the organic solvent is inhibited on the DSA film.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: August 27, 2019
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Masahiko Harumoto, Koji Kaneyama, Yuji Tanaka, Masaya Asai
  • Patent number: 10388873
    Abstract: An evaporation mask is disclosed. The evaporation mask includes a mask frame, a set of first mask strips arranged on the mask frame along a first direction, and a set of second mask strips arranged on the set of first mask strips along a second direction different from the first direction. Each of the second mask strips has sections overlapping the first mask strips. The sections are embedded in respective ones of the first mask strips. Also disclosed is a method of patterning a substrate using the evaporation mask, as well as an organic light-emitting diode display substrate manufactured using the method.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: August 20, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shenchun Chang
  • Patent number: 10381296
    Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a conductive post. The first patterned conductive layer includes a first conductive pad and a second conductive pad. The conductive post is disposed on the first conductive pad. The conductive post includes a first portion and a second portion. The first portion and the second portion of the conductive post are exposed by the first dielectric layer. The first portion of the conductive post has a first width corresponding to a top line width of the first portion and the second portion of the conductive post has a width. The width of the second portion of the conductive post is greater than the first width of the first portion of the conductive post.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: August 13, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Li Chuan Tsai, Chih-Cheng Lee
  • Patent number: 10381837
    Abstract: Photovoltaic systems and related techniques are provided. A method for commissioning a photovoltaic (PV) system may include obtaining data describing an arrangement of two or more components of the PV system; performing a test of the PV system, wherein performing the test includes determining whether the PV system complies with at least one PV system criterion based, at least in part, on at least a portion of the data describing the arrangement of the two or more components of the PV system; and in response to determining that the PV system complies with the at least one PV system criterion, activating the PV system and/or notifying a user of the PV system that the PV system complies with the at least one PV system criterion. The method may further include sending information associated with the PV system to a regulatory entity and/or an operator of an electrical grid.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: August 13, 2019
    Assignee: Fraunhofer USA, Inc.
    Inventors: Christian Hoepfner, Dirk E. Mahling, Matthew Alan Kromer, James R. Perkinson
  • Patent number: 10381489
    Abstract: The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 13, 2019
    Assignees: National University Corporation Hokkaido University, Japan Science and Technology Agency
    Inventors: Takashi Fukui, Katsuhiro Tomioka
  • Patent number: 10380496
    Abstract: Quantum computing assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a quantum computing assembly may include a plurality of dies electrically coupled to a package substrate, and lateral interconnects between different dies of the plurality of dies, wherein the lateral interconnects include a superconductor, and at least one of the dies of the plurality of dies includes quantum processing circuitry.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: August 13, 2019
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Javier A. Falcon, Hubert C. George, Shawna M. Liff, James S. Clarke
  • Patent number: 10374157
    Abstract: A mask for deposition, a method of manufacturing a mask for deposition, and a method of manufacturing a display device, the mask for deposition being coupleable to a frame with tensile force applied to opposite ends of the mask in a first direction and including a first rib portion having a first thickness; and a pattern portion including a plurality of pattern holes through which a deposition material is transmittable, and at least one etch portion, the at least one etch portion having a second thickness that is less than the first thickness and connecting between some of the plurality of pattern holes.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 6, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeongkuk Kim, Minho Moon, Youngmin Moon
  • Patent number: 10366930
    Abstract: A method includes forming a plurality of fins above a substrate. A first placeholder gate electrode is formed above the plurality of fins. The first placeholder gate electrode includes a placeholder material. A first sacrificial gate cut structure of a sacrificial material different than the placeholder material embedded in the first placeholder gate electrode is formed. A portion of the first placeholder gate electrode positioned above the first sacrificial gate cut structure is removed, exposing the first sacrificial gate cut structure. The first sacrificial gate cut structure is removed to define a gate cut cavity extending vertically through the first placeholder gate electrode. A dielectric material is formed in the gate cut cavity to define a gate cut structure. The first placeholder gate electrode is removed to define a first gate cavity segmented by the gate cut structure. A first replacement gate structure is formed in the first gate cavity.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Chanro Park, Min Gyu Sung, Kangguo Cheng, Guillaume Bouche
  • Patent number: 10366941
    Abstract: Provided is a package structure including a substrate, a metal pad, a first polymer layer, a second polymer layer, a redistribution layer (RDL), and a third polymer layer. The metal pad is located on the substrate. The first polymer layer is located on the substrate. The first polymer layer has a first opening which exposes a portion of a top surface of the metal pad. The second polymer layer is located on the first polymer layer. The second polymer layer has a second opening which exposes the portion of the top surface of the metal pad and a first top surface of the first polymer layer. The RDL covers the portion of the top surface of the metal pad and extends onto a portion of the first top surface of the first polymer layer and the second polymer layer. The third polymer layer is located on the RDL.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: July 30, 2019
    Assignee: Winbond Electronics Corp.
    Inventors: Chen-Heng Liu, Yung-Fu Chang
  • Patent number: 10340450
    Abstract: A resistive random access memory (RRAM) structure and its forming method are provided, which includes an interlayer dielectric layer on a substrate. The interlayer dielectric layer is a dielectrics including oxygen. The RRAM structure also includes an oxygen-diffusion barrier layer on the interlayer dielectric layer, and a bottom electrode layer on the oxygen-diffusion barrier layer. The bottom electrode layer includes a first electrode layer, a first oxygen-rich layer on the first electrode layer, and a second electrode layer on the first oxygen-rich layer. The RRAM structure also includes a resistance switching layer on the bottom electrode layer, and a top electrode layer on the resistance switching layer.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 2, 2019
    Assignee: WINBOND ELECTRONICS CORP.
    Inventors: Po-Yen Hsu, Chih-Cheng Fu, Ting-Ying Shen