Patents Examined by Feifei Yeung-Lopez
  • Patent number: 12086690
    Abstract: A quantum computer architecture system, including: a quantum processor, including a plurality of qubits; a first integration apparatus configured to implement an execution signal and aggregation of execution results of a first quantity of qubits on the quantum processor; and a central control apparatus configured to acquire bit information of to-be-executed qubits on the quantum processor and to-be-executed information of each of the to-be-executed qubits, assign the to-be-executed information to one or more the first integration apparatuses according to the bit information and the first quantity, and receive the aggregation of the execution results from the one or more the first integration apparatuses. According to the present disclosure, integration and scalability of a quantum computer can be improved.
    Type: Grant
    Filed: October 17, 2023
    Date of Patent: September 10, 2024
    Assignee: ORIGIN QUANTUM COMPUTING TECHNOLOGY (HEFEI) CO., LTD
    Inventors: Weicheng Kong, Xuebai Li
  • Patent number: 12080687
    Abstract: A unit pixel is provided. The unit pixel includes a transparent substrate, a first light blocking layer disposed on the transparent substrate and having windows that transmit light, an adhesive layer covering the first light blocking layer, a plurality of light emitting devices disposed on the adhesive layer to be arranged on the windows, and a second light blocking layer covering side surfaces of the light emitting devices.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: September 3, 2024
    Assignee: Seoul Viosys Co., Ltd.
    Inventor: Namgoo Cha
  • Patent number: 12080606
    Abstract: The present application provides a method for manufacturing a semiconductor, comprising providing a substrate, on which a first, second and third dielectric layers are successively formed, the third dielectric layer having an initial opening; forming a first deposited layer which at least covers a side wall of the initial opening to form a first mask layer having a first opening; removing the second dielectric layer directly below the first opening to expose a side wall of the second dielectric layer; forming a second deposited layer which at least covers the side wall of the first opening and the exposed side wall of the second dielectric layer, to form a second mask layer having a second opening; removing the first dielectric layer directly below the second opening to expose the substrate; and removing the second mask layer, and forming a trench by etching the substrate.
    Type: Grant
    Filed: December 30, 2021
    Date of Patent: September 3, 2024
    Assignee: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yan Xie, Xuanjun Liu
  • Patent number: 12070307
    Abstract: A sensor device, such as a biosensor, may comprise a polymer substrate, which is structured so as to form sets of microneedles and respective vias. The microneedles extend, each, from a base surface of the substrate. Each of the vias extends through a thickness of the substrate, thereby forming a corresponding set of apertures on the base surface. Each of the apertures is adjacent to a respective one of the microneedles. The device further may comprise two or more electrodes, these including a sensing electrode and a reference electrode. Each electrode may comprise an electrically conductive material layer that coats a region of the substrate, so as to coat at least some of the microneedles and neighboring portions of said base surface. Related devices, apparatuses, and methods of fabrication and use of such devices may be provided.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 27, 2024
    Assignee: International Business Machines Corporation
    Inventors: Neil Ebejer, Ute Drechsler, Patrick Ruch
  • Patent number: 12072464
    Abstract: A motion sensor assembly may include a cover plate configured to be mounted to an electrical box. The cover plate may include a front surface configured to face away from the electrical box and a rear surface opposite the front surface. The cover plate may further include an aperture configured to receive a toggle or rocker type switch. A motion sensor may be coupled to the cover plate. A power source and processor may be operably coupled to the motion sensor. Furthermore, the processor may be operably coupled to a communication device.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: August 27, 2024
    Assignee: TRANSFORM SR BRANDS LLC
    Inventors: Shwetak N. Patel, Matthew Stephen Reynolds
  • Patent number: 12057538
    Abstract: A driving substrate, including: a base; a first insulating layer and first conductive wires on the base; the first insulating layer is provided with openings, the first conductive wires are positioned in the openings, and at any position in a lengthwise direction of the first conductive wires, each side surface of each first conductive wire is in contact with a side surface of the opening, where said each first conductive wire is positioned, at least at a partial height; each first conductive wire includes a seed wire and a growth wire; second conductive wires positioned on a side of the first conductive wires away from the base, each second conductive wire is coupled to one first conductive wire and is provided with a coupling area for coupling a light-emitting unit. A method for manufacturing the driving substrate, a light-emitting substrate and a display device are further provided.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: August 6, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jianguo Wang, Zhanfeng Cao
  • Patent number: 12050401
    Abstract: An imprinting device includes an aligner configured to adjust a relative position between an original plate and a substrate when the original plate including a pattern is moved into contact with the substrate including a transfer target material; a first irradiator configured to irradiate the transfer target material with first light based on an irradiation condition before adjusting the relative position; a second irradiator configured to cure the transfer target material by irradiating the transfer target material with second light after adjusting the relative position; an index acquirer configured to acquire an accuracy index indicating an adjustment accuracy of the adjusted relative position; a memory configured to store data including a plurality of the accuracy indexes acquired for a plurality of the substrates; and a controller configured to adjust the irradiation condition when subsequently using the first irradiator based on the data.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 30, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Motoko Suzuki, Kazuya Fukuhara
  • Patent number: 12051615
    Abstract: A method for manufacturing a semiconductor structure includes: a substrate is provided, an isolation trench being formed on the substrate; a silicon-rich isolation layer is formed in the isolation trench, the silicon-rich isolation layer covering an inner surface of the isolation trench; and an isolation oxide layer is formed in the isolation trench. The isolation oxide layer fills up the isolation trench.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: July 30, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Mengzhu Qiao
  • Patent number: 12046618
    Abstract: A sensor includes a first substrate including at least a first pixel. The first pixel includes an avalanche photodiode to convert incident light into electric charge and includes an anode and a cathode. The cathode is in a well region of the first substrate. The first pixel includes an isolation region that isolates the well region from at least a second pixel that is adjacent to the first pixel. The first pixel includes a hole accumulation region between the isolation region and the well region. The hole accumulation region is electrically connected to the anode.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: July 23, 2024
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yusuke Otake, Akira Matsumoto, Junpei Yamamoto, Ryusei Naito, Masahiko Nakamizo, Toshifumi Wakano
  • Patent number: 12040319
    Abstract: A display device is provided. The display device includes: a substrate; a first electrode located on the substrate; a second electrode located between the substrate and the first electrode; a first light emitting element located on the same layer as the first electrode; and a contact electrode located on the first light emitting element, wherein one end of the first light emitting element contacts the first electrode, and the other end of the first light emitting element contacts the contact electrode.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: July 16, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Woo Lee, Zu Seok Oh, Da Sol Jeong, Kyung Ah Choi, Kyu Ri Hwang
  • Patent number: 12040188
    Abstract: Embodiments of this disclosure provide a photoresist structure, a patterned deposition layer, a semiconductor chip and a manufacturing method thereof According to the method for manufacturing a photoresist structure, a single photoresist is used, a second photoresist layer having an undercut can be obtained by only one development process using a single developing solution, and the size of the undercut can be controlled by the development time, thereby solving the problems such as difficulty in lift-off caused by adhesion of the deposited material to the sidewall of the photoresist structure in traditional lift-off processes.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: July 16, 2024
    Assignee: Tencent Technology (Shenzhen) Company Limited
    Inventors: Wenlong Zhang, Yarui Zheng, Shengyu Zhang
  • Patent number: 12033896
    Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: July 9, 2024
    Assignee: Intel Corporation
    Inventors: Aaron D. Lilak, Christopher J. Jezewski, Willy Rachmady, Rishabh Mehandru, Gilbert Dewey, Anh Phan
  • Patent number: 12034102
    Abstract: An LED light source includes a board, a holder, an LED, a fastener, a lens, a supporter, and an adhesive. The board has a first surface. The holder is arranged on or above the first surface. The LED is arranged on or above the first surface. The fastener fastens the LED to the first surface. The lens has an exterior shape larger than the LED as viewed in a plan view, and is arranged on or above an LED upper surface to refract LED light so as to direct the light outward. The supporter is arranged on an exterior with respect to the LED as viewed in a plan view on a lens surface facing the first surface. The supporter is held by the holder for positioning of the lens at a predetermined position on the first surface. The adhesive bonds the supporter and the board together.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: July 9, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Munetsugu Ehara
  • Patent number: 12034098
    Abstract: An optoelectronic device includes an optoelectronic semiconductor chip having a first and a second semiconductor layer having a first and second conductivity type, respectively; a first and a second current spreading layer; a dielectric reflective layer; and a plurality of first electrical connecting elements. The first semiconductor layer and the second semiconductor layer are stacked. The first current spreading layer and the second current spreading layer are arranged on a side of the first semiconductor layer facing away from the second semiconductor layer. The dielectric reflective layer is arranged between the first semiconductor layer and the first current spreading layer. The plurality of first electrical connecting elements extends through the dielectric reflective layer and is suitable to electrically connect the first semiconductor layer to the first current spreading layer. The second current spreading layer is electrically connected to the second semiconductor layer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: July 9, 2024
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Andreas Leber, Siegfried Herrmann, Christine Rafael
  • Patent number: 12027346
    Abstract: A substrate processing apparatus includes a chamber including a processing room for processing of a substrate using an introduced gas and an exhaust room for exhausting the gas in the processing room, a shield member provided near a side wall of the chamber to separate the processing room and the exhaust room and including a hole allowing the processing room and the exhaust room to communicate with each other, the shield member being driven in a vertical direction, and a hollow relay member connected to a pipe connected to an instrument outside the chamber and configured to be driven in a horizontal direction. When the shield member reaches an upper position, the relay member is driven inwardly of the chamber to be connected to the shield member at its inward end to allow the processing room and the pipe to communicate with each other through the hole.
    Type: Grant
    Filed: July 27, 2021
    Date of Patent: July 2, 2024
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Nobutaka Sasaki, Shin Matsuura
  • Patent number: 12027654
    Abstract: A unit pixel includes a transparent substrate having an upper surface and a lower surface, a plurality of light emitting devices arranged over the upper surface of the transparent substrate, and a reflector disposed between the light emitting devices and the transparent substrate. Light emitted from the light emitting devices is configured to exit to the outside through the upper and lower surfaces of the transparent substrate, and the reflector is configured to reflect light proceeding to the upper surface of the transparent substrate from the inside of the transparent substrate.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: July 2, 2024
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Namgoo Cha, Sangmin Kim, Yeonkyu Park
  • Patent number: 12027569
    Abstract: A dual-sided imaging thin film display structure is provided, comprising a light source, a reflective polarizing element, a basing layer and a linear polarizing element. The reflective polarizing element is disposed on a front surface of the light source, the basing layer is disposed on a back surface of the light source, and the linear polarizing element is further disposed behind the basing layer. A transmission axis of the reflective polarizing element and that of the linear polarizing element are orthogonal, such that a light beam emitted from the light source passes through the reflective polarizing element to form a front image, be reflected by the reflective polarizing element, and passes through the linear polarizing element to form a back image. By employing the present invention, it achieves to provide dual-sided images and interferences between the images are suppressed to obtain superior imaging quality and resolution.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: July 2, 2024
    Assignees: Interface Technology (ChengDu) Co., Ltd., Interface Optoelectronics (Shenzhen) Co., Ltd., General Interface Solution Limited
    Inventors: Che Wen Chiang, Po Lun Chen
  • Patent number: 12022678
    Abstract: A display device having an active region and a non-active region, includes a first substrate, a second substrate, and a sealing layer. The first substrate includes a first substrate layer, a plurality of light-emitting units disposed on the first substrate layer in the active region, and a plurality of dams disposed on the first substrate layer in the non-active region. The second substrate includes a plurality of light conversion units in the active region. The sealing layer is disposed between the first substrate and the second substrate, wherein the sealing layer includes a first portion disposed in the non-active region and a second portion disposed in the active region, and the first portion and the second portion are continuous, wherein at least a part of the first portion of the sealing layer is disposed between at least two of the plurality of dams.
    Type: Grant
    Filed: July 6, 2022
    Date of Patent: June 25, 2024
    Assignee: InnoLux Corporation
    Inventors: Hsiao-Lang Lin, Tsung-Han Tsai
  • Patent number: 12015105
    Abstract: A method and device for electrostatically controlling charges in an electrostatic field effect optoelectronic device by modulating charges in at least one layer of the electrostatic field effect optoelectronic device by providing either a positive bias or a negative bias to a capacitively coupled plate of the electrostatic field effect optoelectronic device thereby adjusting the charge utilization efficiency of the device.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: June 18, 2024
    Assignee: Rochester Institute of Technology
    Inventors: Matthew Hartensveld, Jing Zhang
  • Patent number: 12009459
    Abstract: A light-emitting device, a light-emitting assembly and an integrated circuit (IC) flip-chip are provided. The light-emitting device includes the IC flip-chip, a plurality of light-emitting diode (LED) flip-chips and a substrate. The IC flip-chip includes a plurality of flip-chip pads. The LED flip-chips are spaced apart from the IC flip-chip. The substrate carries the IC flip-chip and the LED flip-chips. The LED flip-chips have a plurality of electrodes, and the flip-chip pads of the IC flip-chip and the electrodes of the LED flip-chips are disposed on the substrate by way of soldering. The LED flip-chips are electrically coupled to the IC flip-chip through the substrate.
    Type: Grant
    Filed: August 1, 2021
    Date of Patent: June 11, 2024
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chen-Hsiu Lin, Min-Hsi Chen