Abstract: A light emitting device package including a base substrate having a front surface and a rear surface, and including a first recess portion recessed from the front surface, a plurality of outer electrodes disposed on the front surface, a light emitting device disposed in the first recess portion and configured to emit light in a direction away from the base substrate, and including a substrate, a light emitting structure disposed on the substrate, and a plurality of bump electrodes disposed on the substrate, and a plurality of connection electrodes connecting the light emitting device to the outer electrodes, in which an upper surface of the bump electrodes and an upper surface of the outer electrodes are disposed on substantially the same plane, and each of the connection electrodes is disposed on one of the bump electrodes and one of the outer electrodes that are adjacent to each other.
Abstract: A structure has a color filter having two or more different types of pixels and an absorption layer including at least one selected from a yellow colorant or a colorant having a maximum absorption wavelength in a wavelength range of 400 to 500 nm, in which the structure has the absorption layer on an optical path of at least one pixel of the pixels of the color filter and on the side through which light is incident on the pixel.
Abstract: A semiconductor device includes an active region on a substrate extending in a first direction, the active region having an upper surface and sidewalls, a plurality of channel layers above the active region to be vertically spaced apart from each other, a gate electrode extending in a second direction to intersect the active region and partially surrounding the plurality of channel layers, and a source/drain region on the active region on at least one side of the gate electrode and in contact with the plurality of channel layers, and extending from the sidewalls of the active region having a major width in the second direction in a first region adjacent to a lowermost channel layer adjacent to the active region among the plurality of channel layer.
January 6, 2020
Date of Patent:
October 19, 2021
Samsung Electronics Co., Ltd.
Sunguk Jang, Kihwan Kim, Sujin Jung, Youngdae Cho
Abstract: A display substrate, a fine metal mask set and a display device are provided, a display substrate includes: first pixels and second pixels alternately arranged in a first direction and a second direction, each of the first pixels includes a first sub-pixel and a second sub-pixel, and each of second pixels includes a third sub-pixel and a second sub-pixel, the second sub-pixels are evenly arranged in a matrix, the first sub-pixel and the third sub-pixel are polygonal, and are alternately arranged in the first direction and the second direction; for one first sub-pixel and one third sub-pixel adjacent to each other in the first direction, a line connecting a vertex of the one first sub-pixel closest to the one third sub-pixel with a vertex of the one third sub-pixel closest to the one first sub-pixel intersects an extension line in the first direction and an extension line in the second direction.
Abstract: An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for additional absorption. In addition, the elevated photosensors reduce the size of the pixel cells while reducing leakage, image lag, and barrier problems.
Abstract: This disclosure relates to quantum electronic devices for storing qubits. In particular, this disclosure relates to a quantum electronic device comprising a carbon nanosphere adapted to store a qubit represented by an electron spin and a control and readout device to set the qubit and read the qubit stored on the carbon nanosphere. Qubits stored on carbon nanospheres have a long electron spin lifetime at room temperature. This disclosure further relates to a method for quantum computing. The method comprises storing a qubit represented by an electron spin on a carbon nanosphere, performing a quantum operation on the qubit to generate a resulting qubit and reading the resulting qubit from the nanosphere. There is further provided a spintronic device comprising multiple carbon nanospheres adapted to provide a qubit represented by an electron spin in that carbon nanosphere and a control device to facilitate interaction between the qubits to perform a quantum operation.
Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to single fin structures and methods of manufacture. The structure includes: an active single fin structure; a plurality of dummy fin structures on opposing sides of the active single fin structure; source and drain regions formed on the active single fin structure and the dummy fin structures; recessed shallow trench isolation (STI) regions between the dummy fin structures and the active single fin structure and below a surface of the dummy fin structures; and contacts formed on the source and drain regions of the active single fin structure with a spacing of at least two dummy fin structures on opposing sides of the contacts.
Abstract: A semiconductor device includes: a first semiconductor layer; a second semiconductor layer including a first dopant of a first conductivity type and a second dopant of a second conductivity type, wherein the first dopant has a doping concentration, and the first conductivity type is different from the second conductivity type; a third semiconductor layer on the second semiconductor layer, wherein the third semiconductor layer includes a third dopant including a doping concentration higher than the doping concentration of the first dopant; and an active region between the first semiconductor layer and the second semiconductor layer; wherein the second semiconductor layer includes a bottom surface facing the active region, and the active region includes a top surface facing the second semiconductor layer, and a distance between the bottom surface of the second semiconductor layer and the top surface of the active region is not less than 2 nm.
Abstract: A stem includes a base member that includes a main body, a raised portion raised from the top surface of the main body, and a through-hole through the main body, a lead that is inserted into the through-hole of the base member and is fixed to the through-hole with a fixing material such that one end of the lead juts out of the top surface of the main body of the base member, and a substrate that is inserted into a gap between the raised portion of the base member and one end of the lead and is attached to the raised portion to be electrically connected to the one end. The lead has a curved surface curving in a direction widening the gap into which the substrate is inserted, or an inclined surface inclined in a direction widening the gap, on a tip of the one end.
Abstract: Embodiments disclosed herein include a processing system and a method of forming a contact. The processing system includes a plurality of process chambers configured to deposit, etch, and/or anneal a source/drain region of a substrate. The method includes depositing a doped semiconductor layer over a source/drain region, forming an anchor layer in a trench, and depositing a conductor in the trench. The method of forming a contact results in reduced contact resistance by using integrated processes, which allows various operations of the source/drain contact formation to be performed within the same processing system.
Abstract: To provide a semiconductor device including a planar transistor having an oxide semiconductor and a capacitor. In a semiconductor device, a transistor includes an oxide semiconductor film, a gate insulating film over the oxide semiconductor film, a gate electrode over the gate insulating film, a second insulating film over the gate electrode, a third insulating film over the second insulating film, and a source and a drain electrodes over the third insulating film; the source and the drain electrodes are electrically connected to the oxide semiconductor film; a capacitor includes a first and a second conductive films and the second insulating film; the first conductive film and the gate electrode are provided over the same surface; the second conductive film and the source and the drain electrodes are provided over the same surface; and the second insulating film is provided between the first and the second conductive films.
September 22, 2020
Date of Patent:
August 31, 2021
Semiconductor Energy Laboratory Co., Ltd.
Abstract: A method of peeling a mother protective film from a mother display panel includes: laminating the mother display panel and the mother protective film, the mother display panel including a plurality of display cells each including a display area and a peripheral area around the plurality of display cell; forming a target area and a dummy area in the mother protective film by forming a cutting line in a closed loop shape enclosing the target area corresponding to each of the display cells and a first additional cutting line in a first direction near the cutting line; physically peeling off the dummy area from the mother display panel, including: primarily peeling off a portion of the mother protective film adjacent to the first additional cutting line; and secondarily peeling off rest of the mother protective film from the mother display panel along the cutting line.
Abstract: A semiconductor device includes a substrate, a source/drain structure, a source/drain contact, a gate structure, a first etching stop layer, and a via contact. The source/drain structure is over the substrate. The source/drain contact is over the source/drain contact. The gate structure is over the substrate. The first etching stop layer is over the gate structure, in which the first etching stop layer includes a first portion and a second portion, and a thickness of the first portion is lower than a thickness the second portion. The via contact extends along a top surface of the first portion of the first etching stop layer to a sidewall of the second portion of the first etching stop layer.
Abstract: Disclosed is a light emitting apparatus including: a first substrate having light transmissive property and flexibility with a conductive layer; a second substrate having light transmissive property and flexibility and arranged to face the first substrate; a plurality of light emitting elements including an electrode connected to the conductive layer and arranged between the first and second substrates; and a resin layer having light transmissive property and flexibility and arranged between the first and second substrates to hold the plurality of light emitting elements. A temperature for a maximum mechanical loss tangent tan ? in dynamic viscoelasticity of the resin layer is 117° C. or higher.
Abstract: A semiconductor device includes an active region extending on a substrate in a first direction and including an impurity region, a plurality of channel layers vertically spaced apart from each other on the active region, a gate structure extending on the substrate in a second direction to intersect the active region and the plurality of channel layers, and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and in contact with the plurality of channel layers, a barrier layer including a first barrier layer spaced apart from an upper surface of the active region and being disposed in the active region, and second barrier layers respectively disposed below the plurality of channel layers, and a contact plug connected to the source/drain region.
Abstract: According to a flexible light-emitting device production method of the present disclosure, after an intermediate region (30i) and flexible substrate regions (30d) of a plastic film (30) of a multilayer stack (100) are divided from one another, the interface between the flexible substrate regions (30d) and a glass base (10) is irradiated with lift-off light. The multilayer stack (100) is separated into a first portion (110) and a second portion (120) while the multilayer stack (100) is in contact with a stage (210). The first portion (110) includes a plurality of light-emitting devices (1000) which are in contact with the stage (210). The light-emitting devices (1000) include a plurality of functional layer regions (20) and the flexible substrate regions (30d). The second portion (120) includes the glass base (10) and the intermediate region (30i).
Abstract: A semiconductor package includes a frame having a through-hole, and a first semiconductor chip disposed in the through-hole of the frame and having an active surface on which a connection pad is disposed, an inactive surface opposing the active surface, and a side surface connecting the active and inactive surfaces. A first encapsulant covers at least a portion of each of the inactive surface and the side surface of the first semiconductor chip. A connection structure has a first surface having disposed thereon the active surface of the first semiconductor chip, and includes a redistribution layer electrically connected to the connection pad of the first semiconductor chip. A first passive component is disposed on a second surface of the connection structure opposing the first surface, the first passive component being electrically connected to the redistribution layer and having a thickness greater than a thickness of the first semiconductor chip.
June 27, 2019
Date of Patent:
July 20, 2021
SAMSUNG ELECTRO-MECHANICS CO., LTD.
Chui Kyu Kim, Dae Hyun Park, Jung Ho Shim, Jae Hyun Lim, Mi Ja Han, Sang Jong Lee, Han Kim
Abstract: An active matrix substrate according to an embodiment of the present invention includes: a substrate; a plurality of first TFTs supported by the substrate and provided in a non-displaying region; and a peripheral circuit including the plurality of first TFTs. Each first TFT includes: a first gate electrode provided on the substrate; a first gate insulating layer covering the first gate electrode; a first oxide semiconductor layer opposed to the first gate electrode via the first gate insulating layer; and a first source electrode and a first drain electrode connected to a source contact region and a drain contact region of the first oxide semiconductor layer. Each first TFT has a bottom contact structure. A first region of the first gate insulating layer that overlaps the channel region has a thickness which is smaller than a thickness of a second region of the first gate insulating layer that overlaps the source contact region and the drain contact region.
Abstract: Capacitor structures including a first island of a first conductive region and a second island of the first conductive region having a first conductivity type, an island of a second conductive region having a second conductivity type different than the first conductivity type, a dielectric overlying the first island of the first conductive region, a conductor overlying the dielectric, and a terminal of a diode overlying the second island of the first conductive region and overlying the island of the second conductive region.
Abstract: In view of the high-temperature issues in III-N layer growth process, embodiments described herein use layered structure including a rare earth oxide (REO) or rare earth nitride (REN) buffer layer and a polymorphic III-N-RE transition layer to transit from a REO layer to a III-N layer. In some embodiments, the piezoelectric coefficient of III-N layer is increased by introduction of additional strain in the layered structure. The polymorphism of RE-III-N nitrides can then be used for lattice matching with the III-N layer.
November 19, 2019
Date of Patent:
July 13, 2021
Rytis Dargis, Andrew Clark, Rodney Pelzel, Michael Lebby, Robert Yanka