Abstract: In an embodiment of the present disclosure, a device structure includes a fin structure, a gate on the fin structure, and a source and a drain on the fin structure, where the gate is between the source and the drain. The device structure further includes an insulator layer having a first insulator layer portion adjacent to a sidewall of the source, a second insulator layer portion adjacent to a sidewall of the drain, and a third insulator layer portion therebetween adjacent to a sidewall of the gate, and two or more stressor materials adjacent to the insulator layer. The stressor materials can be tensile or compressively stressed and may strain a channel under the gate.

Abstract: A lighting device disclosed in an embodiment of the invention includes a substrate; a plurality of light emitting devices disposed on the substrate; a resin layer disposed on the substrate and the plurality of light emitting devices and including a lens portion; and a plurality of recess portions that seal a periphery of each of the light emitting devices and form a space spaced apart between the lens portion and the substrate. The resin layer includes a flat upper surface and a lower surface disposed on the substrate, and the lens portion may include a protrusion portion protruding toward a central portion of the light emitting device, a first incident surface having a convex curved surface around the protrusion portion, and a second incident surface extending perpendicular to the substrate from a lower portion of the first incident surface.

Abstract: Methods for manufacturing semiconductor structures are provided. The method includes alternately stacking sacrificial layers and semiconductor layers over a substrate to form a semiconductor stack and forming a first mask structure and a second mask structure over the semiconductor stack. In addition, a width of the first mask structure is substantially equal to a width of the second mask structure. The method further includes forming spacers on sidewalls of the second mask structure and patterning the semiconductor stack to form a first fin structure overlapping the first mask structure and a second fin structure overlapping the second mask structure and the spacers. In addition, the first fin structure has a first width and the second fin structure has a second width different from the first width. The method further includes removing the sacrificial layers to form first nanostructures and second nanostructures.

Abstract: Disclosed are an oxide semiconductor thin film transistor and a method of fabricating the same. An oxide semiconductor thin film transistor according to an embodiment of the present disclosure includes a substrate; a first gate electrode formed on the substrate; a gate insulator formed on the first gate electrode; an oxide semiconductor layer formed on the gate insulator; source and drain electrodes formed by depositing carbon nanotubes (CNTs) and a metal electrode on the formed the oxide semiconductor layer and patterning the deposited CNTs and metal electrode such that the source electrode and the drain electrode are spaced apart from each other; and a passivation layer formed on the formed source and drain electrodes, wherein the source and drain electrodes serve to prevent diffusion of a metal of the metal electrode into the formed oxide semiconductor layer, due to the CNTs of the source and drain electrodes.

Abstract: A light emitting device package according to an embodiment may include: a first frame including a first opening passing through upper and lower surfaces, and a second frame spaced apart from the first frame and including a second opening; first and second conductive layers disposed in the first and second openings, respectively; a body disposed between the first and second frames; a first resin disposed on the body; and a light emitting device disposed on the first resin. According to an embodiment, the light emitting device may include a first bonding part electrically connected with the first frame and a second bonding part spaced apart from the first bonding part and electrically connected with the second frame, and the first and second bonding parts may be disposed on the first and second openings, respectively.

Abstract: A method of manufacturing a light-emitting device includes: mounting a light-emitting element on a mounting board; placing a light-shielding frame on a sheet, the light-shielding frame defining an opening and comprising at least one narrow portion having a width that is smaller than that of another portion of the light-shielding frame in a top view; applying a light-reflective resin on at least the narrow portion of the light-shielding frame; forming a light-guiding supporting member; and bonding the second surface of a light-transmissive member of the light-guiding supporting member to an upper surface of the light-emitting element so as to fix the light-guiding supporting member on or above the light-emitting element.

Abstract: A surface-emitting light source includes a plurality of light-emitting regions each of which includes light sources, wherein each of the plurality of light-emitting regions can be turned on individually. Each of the light-emitting regions is adjacent to each other and includes a light-guide portion that is provided in adjacent light-emitting regions and covers the light sources, and a light-reflective member disposed below the light-guide portion. The light-reflective member has a first wall portion disposed at the outer periphery of each of the light-emitting regions. The first wall portion includes one or more unit first wall portions each of which corresponds to a respective one of the light sources located at the outer periphery of each of the light-emitting regions. The unit first wall portion located at the two adjacent light-emitting regions has a central portion having a height smaller than a height of both end portions.

Abstract: Short channel, horizontal gate-all-around (GAA) nanostructure (e.g., nanosheet, nanowire, or the like) transistors, methods of manufacturing and devices formed with the GAA transistors are disclosed herein. According to some methods, the GAA transistors are formed with a guard band for preventing diffusion of APT doping into the channel region, with shallow source/drain depths, and/or with epitaxial growth of the device channel regions after well and APT implantation in the substrate. As such, the GAA transistors are formed to mitigate issues such as bottom sheet voltage threshold (Vt) shift, junction leakage, APT dopant out-diffusion, well proximity effect, APT implant contamination that may be induced by anti-punch through (APT) doping diffusion during fabrication of gate all-around (GAA) transistors. The GAA transistors and methods of manufacturing, however, may be utilized in a wide variety of ways, and may be integrated into a wide variety of devices and technologies.

Abstract: The light emitting device package disclosed in the embodiment includes first and second frames spaced apart from each other; a body disposed between the first and second frames; a light emitting device including a first bonding portion and a second bonding portion on a lower portion thereof; and a first resin disposed between the body and the light emitting device, wherein the first frame includes a first protruding portion facing the first bonding portion of the light emitting device, and the second frame includes a second protruding portion facing the second bonding portion of the light emitting device, and including a first conductive layer between the first bonding portion and the first protruding portion and a second conductive layer between the second bonding portion and the second protruding portion.

Abstract: A semiconductor device includes a semiconductor layer with opposing first and second main surfaces and a first column extending from the first main surface and having a first concentration of a dopant of the first conductivity type. A trench with a sidewall and bottom extends at least partially through the semiconductor layer from the first main surface. A second column between the trench sidewall and the first column has a second concentration of a dopant of a second conductivity type and is formed in the semiconductor layer and extends from the first main surface. A trench oxide layer is in contact with at least the trench sidewall and the trench bottom. A trench nitride layer covers the trench oxide layer at least on the trench sidewall. A dielectric seal material seals the trench proximate the first main surface of the semiconductor layer such that the trench is air-tight.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first fin structure, a second fin structure, a third fin structure, and a fourth fin structure formed over a substrate. The semiconductor structure further includes first nanostructures, second nanostructures, third nanostructures, and fourth nanostructures. The semiconductor structure further includes a first gate structure wrapping around the first nanostructures and the second nanostructures, and a second gate structure wrapping around the third nanostructures and the fourth nanostructures. In addition, a first lateral distance between the first fin structure and the second fin structure is shorter than a second lateral distance between the third fin structure and the fourth fin structure, and the first fin structure and the second fin structure are narrower than the third fin structure and the fourth fin structure.

Abstract: A multi-COB-LED lighting module includes a submount; and a plurality of clusters of LED-chips that emit light radiation in respective emission bands, wherein each LED-chip cluster includes a plurality of LED-chips arranged on the submount by chip on board technology and emit light radiation in a respective emission band, and at least two LED-chips of at least a first LED-chip cluster each borders with a plurality of LED-chips belonging to one or more clusters of LED-chips different from the first LED-chip cluster and connect one to the other by at least a wire bond that extends above one or more of the adjoining LED-chips.

Abstract: A semiconductor package including an insulating encapsulation, an integrated circuit component, and conductive elements is provided. The integrated circuit component is encapsulated in the insulating encapsulation, wherein the integrated circuit component has at least one through silicon via protruding from the integrated circuit component. The conductive elements are located on the insulating encapsulation, wherein one of the conductive elements is connected to the at least one through silicon via, and the integrated circuit component is electrically connected to the one of the conductive elements through the at least one through silicon via.

Abstract: A spin orbit torque (SOT) memory device includes an SOT electrode on an upper end of an MTJ device. The MTJ device includes a free magnet, a fixed magnet and a tunnel barrier between the free magnet and the fixed magnet and is coupled with a conductive interconnect at a lower end of the MTJ device. The SOT electrode has a footprint that is substantially the same as a footprint of the MTJ device. The SOT device includes a first contact and a second contact on an upper surface of the SOT electrode. The first contact and the second contact are laterally spaced apart by a distance that is no greater than a length of the MTJ device.

Abstract: An optical semiconductor device package includes a circuit board in which a first metal, a second metal, and a third metal are sequentially stacked in an optical semiconductor element mounting region. The first metal has a first standard electrode potential. The second metal is disposed on a portion of an upper surface of the first metal and has a second standard electrode potential that is greater than the first standard electrode potential. The third metal is disposed on the upper surface of the first metal and an upper surface of the second metal and has a third standard electrode potential that is greater than the first standard electrode potential and less than the second standard electrode potential.

Abstract: A memory cell includes a heating element topped with a phase-change material. Two first silicon oxide regions laterally surround the heating element along a first direction. Two second silicon oxide regions laterally surround the heating element along a second direction orthogonal to the first direction. Top surfaces of the heating element and the two first silicon oxide regions are coplanar such that the heating element and the two first silicon oxide regions have a same thickness.

Abstract: An emissive display device including LEDs, including a plurality of pixels, each including: an elementary control cell formed inside and on top of a semiconductor substrate; a first LED capable of emitting in a first wavelength range, arranged on the upper surface of the elementary control cell and having a first conduction region connected to a first connection pad of the elementary control cell; and a second LED capable of emitting in a second wavelength range, having a surface area smaller than that of the first LED, arranged on the upper surface of the first LED opposite a central region of the first LED, and having a first conduction region connected to a second connection pad of the elementary control cell via a first conductive via crossing the first LED.

Abstract: A light emitting device includes a mount board that includes a wiring pattern on an upper surface, and light emitting elements that are mounted at corresponding one of mounting positions on the wiring pattern to be connected in series and/or in parallel to each other through the wiring pattern. The light emitting elements each include a pair of electrodes on a back surface side thereof. The mounting positions include four or more connection terminals that are electrically separated from each other to connect the electrodes of their corresponding light emitting element to each other. Series connection and parallel connection numbers are determined in accordance with orientations of the light emitting elements in which each electrode straddles at least adjacent two of the four or more connection terminals that are spaced away from and adjacent to each other.

Abstract: Provided is a display apparatus including a substrate having a display area including a main pixel, and a sensor area including a sub-pixel and a transmission portion, a plurality of first lines arranged in the sensor area, extending in a first direction, and bypassing the transmission portion, and a first electrode layer under the plurality of first lines, between the sub-pixel and the transmission portion, and at least partially overlapping a spacing region between the plurality of first lines.

Abstract: A display panel and a method of manufacturing a display panel are provided. In a solution, a plurality of grooves are formed on at least one metal layer by an etching process, and a connection portion and the at least one metal layer are connected by an adhesive. The adhesive can flow into the grooves during a bonding process to form a plurality of protrusions to fill the grooves, thereby increasing a contact area with the at least one metal layer and increasing bonding strength between the adhesive and the at least one metal layer. It is possible to avoid poor soldering, dark spots, and the like of a light emitting device.