Abstract: An electronic apparatus includes a first board, a second board, a housing, and a first thermal conductive assembly. The housing accommodates the first board and the second board. The first thermal conductive assembly connects a face of the first board, the face of the first board fronting a region between the first board and the second board, to a first face of the housing or a second face of the housing. The first face is opposed to the first board, the second face is opposed to the second board.

Abstract: A device includes a die with perimeters associated therewith, a substrate, and a test channel. The die is coupled to the substrate via a plurality of C4 bumps on a first side of the substrate. The substrate has connections on a second side of the substrate, opposite to the first side. A first connection connects a C4 bump on the first side of the substrate to a connection on the second side using a metal layer. The test channel is positioned within the substrate and further positioned outside of the perimeter of the die coupled to the substrate. The test channel is positioned at substantially a same depth as the metal layer of the first connection. A probe connecting to the test channel via pads positioned on a same side of the substrate that provides electrical characteristics that is substantially the same as electrical characteristics of the first connection.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: Embodiments described herein generally relate to an electronics assembly that includes a semiconductor device, a substrate layer, a first mesh layer and a second mesh layer. Jet channels that have a first inner diameter are disposed within the substrate layer. The first mesh layer includes a first plurality of pores that have a perimeter opening. The second mesh layer includes a second plurality of pores that have a second inner diameter. The jet channels, the first and the second plurality of pores are concentric to create a fluid path for a fluid to impinge a first device surface of the semiconductor device. The second inner diameter is smaller than the perimeter opening and the first inner diameter of the substrate layer such that a cooling fluid velocity increases when flowing from the substrate layer through the second mesh layer.

Abstract: In one example, a semiconductor device structure relates to an electronic device, which includes a device top surface, a device bottom surface opposite to the device top surface, device side surfaces extending between the device top surface and the device bottom surface, and pads disposed over the device top surface. Interconnects are connected to the pads, and the interconnects first regions that each extend from a respective pad in in an upward direction, and second regions each connected to a respective first region, wherein each second region extends from the respective first region in a lateral direction. The interconnects comprise a redistribution pattern on the pads. Other examples and related methods are also disclosed herein.

Abstract: The present disclosure provides a current-driven display, including a substrate and a first electrode layer stacked on the substrate in a stacking direction. The substrate includes a plurality of light-emitting units and a spacer separating each of the plurality of light-emitting units from one another. The first electrode layer includes a first region and a second region. The first region and the second region contact one of the plurality of light-emitting units, respectively, and are separated by the spacer. The current-driven display further includes a second electrode layer, which equipotentially connects the first region and the second region across the spacer. The present disclosure also provides a method for producing a current-driven display.

Abstract: A semiconductor device includes a power module unit, a fin base, and a plurality of radiator fins. The power module unit and the fin base are integrated together, with a recess-projection portion formed on the power module unit being fitted to a recess-projection portion formed on the fin base. The plurality of radiator fins are integrally fitted on a heat radiation diffusion portion of the fin base.

Abstract: Semiconductor packages having a die electrically connected to an antenna by a coaxial interconnect are described. In an example, a semiconductor package includes a molded layer between a first antenna patch and a second antenna patch of the antenna. The first patch may be electrically connected to the coaxial interconnect, and the second patch may be mounted on the molded layer. The molded layer may be formed from a molding compound, and may have a stiffness to resist warpage during fabrication and use of the semiconductor package.

Abstract: A memory device includes a channel, a control gate electrode, and at least one charge storage element located between the channel and the control gate electrode. The control gate electrode includes a first electrically conductive layer, a second electrically conductive layer and a ferroelectric material layer located between the first electrically conductive layer and the second electrically conductive layer.

Abstract: A semiconductor memory device comprising a substrate including a cell region, first and second contact regions, and a bit peripheral circuit region disposed between the first and second contact regions. A first stack structure is disposed on the cell region and the first contact region. A second stack structure is disposed on the cell region and the second contact region. A peripheral transistor is disposed on the bit peripheral circuit region and is electrically connected to the first and second stack structures. Each of the first and second stack structures comprises semiconductor patterns vertically stacked on the cell region, and conductive lines having connection with the semiconductor patterns and extending along a first direction from the cell region onto corresponding first and second contact regions. The conductive lines have stepwise structures on the first and second contact regions.

Abstract: A three-dimensional memory device includes a plurality of conductive layers and insulating layers alternately formed to define a multi-layer stacked structure. The multi-layer stacked structure includes a stair region and an non-stair region, the stair region includes a plurality of steps, each step includes an immediately-adjacent pair of the conductive layers and insulating layers. A plurality of memory structures are located in the non-stair region, and each memory structure passes through the conductive layers and the insulating layers. A fishbone dielectric structure includes a main bone and a plurality of side bones extending from the main bone in the stair region, wherein the main bone crosses the memory structures in the non-stair region.

Abstract: A package structure and method for forming the same are provided. The package structure includes a first interconnect structure formed over a first substrate, and the first interconnect structure includes a first metal layer. The package structure further includes a second interconnect structure formed over a second substrate. The package structure includes a bonding structure between the first interconnect structure and the second interconnect structure. The bonding structure includes a first intermetallic compound (IMC) and a second intermetallic compound (IMC), a portion of the first IMC protrudes from the sidewall surfaces of the second IMC, and there could be a grain boundary between the first IMC and the second IMC.

Abstract: Various packages and methods of forming packages are discussed. According to an embodiment, a package includes a processor die at least laterally encapsulated by an encapsulant, a memory die at least laterally encapsulated by the encapsulant, and a redistribution structure on the encapsulant. The processor die is communicatively coupled to the memory die through the redistribution structure. According to further embodiments, the memory die can include memory that is a cache of the processor die, and the memory die can comprise dynamic random access memory (DRAM).

Abstract: A bonding wire for connecting a first pad to a second pad is provided. The bonding wire includes a ball part bonded to the first pad, a neck part formed on the ball part, and a wire part extending from the neck part to the second pad. Less than an entire portion of a top surface of the neck part is covered by the wire part, and the wire part is in contact with the neck part, the ball part, and the first pad.

Abstract: One illustrative method disclosed herein includes, among other things, selectively forming a sacrificial material on an upper surface of a top electrode of a memory cell, forming at least one layer of insulating material around the sacrificial material and removing the sacrificial material so as to form an opening in the at least one layer of insulating material, wherein the opening exposes the upper surface of the top electrode. The method also includes forming an internal sidewall spacer within the opening in the at least one layer of insulating material and forming a conductive contact structure that is conductively coupled to the upper surface of the top electrode, wherein a portion of the conductive contact structure is surrounded by the internal sidewall spacer.

Abstract: A display device includes a substrate, a display area located over the substrate and including a plurality of pixels, a non-display area arranged outside the display area, a first power voltage line corresponding to one side of the display area in the non-display area and including a first conductive layer and a second conductive layer arranged over the first conductive layer, a second power voltage line spaced apart from the first power voltage line in the non-display area, a first dam unit surrounding the display area and overlapping the second power voltage line in a plan view, a second dam unit arranged outside the first dam unit, and a third dam unit arranged between the display area and the first dam unit and overlapping the first conductive layer and the second conductive layer of the first power voltage line in the plan view.

Abstract: Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement comprises a first guard ring surrounding at least a portion of a device, and a first poly layer formed over the first guard ring.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: There is provided a semiconductor device including a first gate pattern on a semiconductor substrate, a second gate pattern adjacent to a side surface of the first gate pattern via an ONO film, and an active region located just below the second gate pattern via the ONO film. Here, an element isolation region is formed just below the first gate pattern. In this manner, capacitance between the first gate pattern and the semiconductor substrate and capacitance between the first and second gate patterns are prevented from being measured when measuring capacitance between the second gate pattern which is an upper electrode and the active region which is a lower electrode in order to measure a film thickness of the ONO film just below the second gate pattern.

Abstract: Semiconductor packages including package substrates having polymer-derived ceramic cores are described. In an example, a package substrate includes a core layer including a polymer-derived ceramic. The polymer-derived ceramic may include filler particles to control shrinkage and reduce warpage of the core layer during fabrication and use of the package substrate. The core layer may include counterbores or blind holes to embed a contact pad or an electrical interconnect in the core layer. A semiconductor die may be mounted on the package substrate and may be electrically connected to the contact pad or the electrical interconnect.