Patents Examined by Fetsum Abraham
  • Patent number: 7391055
    Abstract: A highly reliable capacitor, a semiconductor device having high operating performance and reliability, and a manufacturing method thereof are provided. A capacitor formed of a first conductive film 102, a dielectric 103 made of an insulating material, and a second conductive film 104 is characterized in that a pin hole 106 formed by chance in the dielectric 103 is filled up with an insulating material (filler) 107 made of a resin material. This can prevent short circuit between the first conductive film 102 and the second conductive film 104. The capacitor is used as a storage capacitor provided in a pixel of a semiconductor device.
    Type: Grant
    Filed: May 12, 2000
    Date of Patent: June 24, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Satoshi Murakami, Yoshiharu Hirakata, Etsuko Fujimoto, Yu Yamazaki, Shunpei Yamazaki
  • Patent number: 7196395
    Abstract: The object is the present invention is to provide a semiconductor device including a circuit employing two or more field-effect transistor that are desired to have equal characteristics, capable of realizing high reliability and superior transistor characteristics. The transistors which are desired to have equal characteristics are placed in the semiconductor device so as to have the same STI trench width (the width of shallow trench isolation adjacent to an active in which the transistor is formed). By such composition, stress growing in the active due to the shallow trench isolation is equalized among the transistors and thereby the characteristics of the transistors can be equalized.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: March 27, 2007
    Assignee: Renesas Technology Corporation
    Inventors: Yukihiro Kumagai, Hideo Miura, Hiroyuki Ohta, Michihiro Mishima, Katsuyuki Nakanishi
  • Patent number: 7161178
    Abstract: There is provided a combination of doping process and use of side walls which allows the source and drain of a thin film transistor of an active matrix circuit to be doped with only one of N-type and P-type impurities and which allows the source and drain of a thin film transistor used in a peripheral circuit of the same conductivity type as that of the thin film transistor of the active matrix circuit to include both of N-type and P-type impurities. Also, a thin film transistor in an active matrix circuit has offset regions by using side walls, and another thin film transistor in a peripheral circuit has a lightly doped region by using side walls.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: January 9, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideomi Suzawa
  • Patent number: 7151278
    Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD?V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: December 19, 2006
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shou Nagao, Munehiro Azami, Yoshifumi Tanada
  • Patent number: 7138722
    Abstract: Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.
    Type: Grant
    Filed: February 15, 2005
    Date of Patent: November 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Toshio Miyamoto, Asao Nishimura, Koki Noguchi, Satoshi Michishita, Masashi Horiguchi, Masaharu Kubo, Kazuyoshi Shiba
  • Patent number: 7138659
    Abstract: A light emitting diode (LED) assembly with a vented printed circuit board is disclosed. A printed circuit board assembly may include a plurality of LED modules disposed in an array with a multilayered substrate and a plurality of vents. The multilayer substrate may include a thermal cooling layer which is in thermal communication with the LED modules for heat dissipation. The multilayer substrate may include one or more electrical power layers in electrical communication with the LED modules for energizing the LEDs. The multilayered substrate may have an external insulating layer that includes a plurality of fluid apertures configured for fluid communication with the thermal cooling layer.
    Type: Grant
    Filed: May 18, 2004
    Date of Patent: November 21, 2006
    Assignee: OnScreen Technologies, Inc.
    Inventors: Robert Bogdan Raos, Nilesh Thakor Desai, Steven Flank
  • Patent number: 7135732
    Abstract: In order to supply a semiconductor device having high-reliability, there are used a first capacitor electrode, a capacitor insulating film formed in contact with the first capacitor electrode and mainly composed of titanium oxide, and a second capacitor electrode formed in contact with the capacitor insulating film, and there is used a conductive oxide film mainly composed of ruthenium oxide or iridium oxide for the first capacitor electrode and the second capacitor electrode. Alternatively, there is used a gate insulating film having a titanium silicate film and titanium oxide which suppress leakage current.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: November 14, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Tomio Iwasaki, Hiroshi Moriya, Hideo Miura, Shuji Ikeda
  • Patent number: 7129570
    Abstract: An electronic component includes at least one semiconductor chip, which has an active chip top side with contact areas and has a chip rear side arranged on a carrier top side of a circuit carrier. The circuit carrier and the chip top side are covered by a common rewiring layer having external contact areas at a different level. The different level is matched to a common level of external contact top sides by means of different heights of in part compliant external contacts.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: October 31, 2006
    Assignee: Infineon Technologies AG
    Inventor: Georg Meyer-Berg
  • Patent number: 7126169
    Abstract: The present invention provides a semiconductor element in which the field-effect transistor and the Schottky diode are arranged such that a depletion layer stemming from the Schottky diode is superimposed on a depletion layer stemming from a junction between a second conductivity type semiconductor constituting the field-effect transistor and a drift region (first conductivity type semiconductor) in an off-state. Furthermore, the present invention provides a semiconductor element in which the field-effect transistor and the Schottky diode are arranged so that a second conductivity type semiconductor other than the second conductivity type semiconductor constituting the field-effect transistor is not interposed between the electric field effect transistor and the Schottky diode. According to preferable embodiments of the present invention, the reverse recovery time due to a parasitic diode can be reduced by providing the Schottky diode such that the element area of the semiconductor element is not increased.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: October 24, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Makoto Kitabatake
  • Patent number: 7109517
    Abstract: Subwavelength random and periodic microscopic structures are used to enhance light absorption and tolerance for ionizing radiation damage of thin film and photodetectors. Diffractive front surface microscopic structures scatter light into oblique propagating higher diffraction orders that are effectively trapped within the volume of the photovoltaic material. For subwavelength periodic microscopic structures etched through the majority of the material, enhanced absorption is due to waveguide effect perpendicular to the surface thereof. Enhanced radiation tolerance of the structures of the present invention is due to closely spaced, vertical sidewall junctions that capture a majority of deeply generated electron-hole pairs before they are lost to recombination. The separation of these vertical sidewall junctions is much smaller than the minority carrier diffusion lengths even after radiation-induced degradation.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: September 19, 2006
    Inventor: Saleem H. Zaidi
  • Patent number: 7109554
    Abstract: In a semiconductor device having an N-channel MOS transistor and a P-channel MOS transistor, each of the N-channel and P-channel MOS transistors is made up of a polycrystal silicon layer, a gate insulating film, and a gate electrode containing a gate polysilicon on a glass substrate. A method of manufacturing the semiconductor device includes the steps of injecting an impurity into the gate polysilicon at a same time as or in a different step of impurity injection at a time of formation of source/drains of the MOS transistors or formation of an LDD (Lightly Doped Drain), to make an N-type of a gate polysilicon in the N-channel MOS transistor and make a P-type of a gate polysilicon in the P-channel MOS transistor and, furthermore, setting a thickness of the polycrystal silicon layer less than the width of a depletion layer which occurs when an inversion channel is formed. Thus, fluctuations in values of threshold voltages of the MOS transistors are reduced to realize low-voltage driving.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: September 19, 2006
    Assignee: NEC Corporation
    Inventor: Mitsuasa Takahashi
  • Patent number: 7105371
    Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: September 12, 2006
    Assignee: California Institute of Technology
    Inventors: Eric R. Fossum, Sunetra Mendis, Sabrina E. Kemeny
  • Patent number: 7102159
    Abstract: An image sensor package having at least one chip supporting bar secured to a top surface of an image sensor chip. The thickness of the chip supporting bar is absorbed within a vertical dimension of wire loops that connect bonding pads to leads so that the chip supporting bar does not contribute to the thickness of the image sensor package. An exposed back surface of the image sensor chip enhances thermal dissipation.
    Type: Grant
    Filed: June 12, 2004
    Date of Patent: September 5, 2006
    Assignee: Macronix International Co., Ltd.
    Inventors: Chen Jung Tsai, Chih-Wen Lin
  • Patent number: 7098489
    Abstract: A plurality of N-type diffusion layers are formed a specified distance apart on a P-type semiconductor layer. A P-type leak prevention layer formed between at least N-type diffusion layers prevents leaking between the diffusion layers. A dielectric film is formed in at least a light incident area on a P-type semiconductor layer including the diffusion layers and the leak prevention layer. Accordingly, provided are a split type light receiving element positively functioning as a split type light receiving element even when charge is accumulated in the dielectric film and having a uniform sensitivity throughout the entire area on a light receiving surface, and a circuit-built-in light receiving element and an optical disk device using the split type light receiving element.
    Type: Grant
    Filed: July 3, 2002
    Date of Patent: August 29, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tatsuya Morioka, Shigeki Hayashida, Yoshihiko Tani, Isamu Ohkubo
  • Patent number: 7098480
    Abstract: Disclosed is a simplified method for manufacturing a liquid crystal display. A gate wire including a gate line, a gate pad, and a gate electrode are formed on a substrate. A gate insulating layer, a semiconductor layer, and an ohmic contact layer are sequentially deposited, and a photoresist layer is coated thereon. The photoresist layer is exposed to light through a mask and developed to form a photoresist pattern. At this time, a first portion of the photoresist pattern which is located between the source electrode and the drain electrode is thinner than a second portion which is located on the data wire, and the photoresist layer is totally removed on other parts. The thin portion is made by controlling the amount of irradiating light or by a reflow process to form a thin portion, and the amount of light is controlled by using a mask that has a slit, a small pattern smaller than the resolution of the exposure device, or a partially transparent layer.
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: August 29, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Gyu Kim, Jong-Soo Yoon
  • Patent number: 7098500
    Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.
    Type: Grant
    Filed: July 8, 2005
    Date of Patent: August 29, 2006
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Jun Zeng
  • Patent number: 7098522
    Abstract: A high voltage device. A high voltage MOS transistor is applied in the ESD protection device to the structure of which a doped region is added, generating a parasitic semiconductor controlled rectifier (SCR) having a shorter discharge path such that the SCR has faster response enhancing ESD protection.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: August 29, 2006
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Geeng-Lih Lin, Yeh-Ning Jou, Ming-Dou Ker
  • Patent number: 7098119
    Abstract: A method is disclosed for forming a semiconductor device using strained silicon. After forming a first substrate material with a first natural lattice constant on a device substrate and a second substrate material with a second natural lattice constant on the first substrate material, a channel, source and drain regions of a field effective transistor are further defined using the first and second substrate materials. After implanting one or more impurity materials to the source and drain regions, and the transistor goes through an annealing process using a high speed heat source other than a Tungsten-Halogen lamp.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: August 29, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Chung-Hu Ke, Wen-Chin Lee, Chenming Hu
  • Patent number: 7098481
    Abstract: In a semiconductor device having a plurality of thin film transistors and matrix wiring lines formed on a substrate, the matrix wiring lines are electrically connected via resistors in order to prevent electrostatic destructions during a panel manufacture process and improve a manufacture yield.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: August 29, 2006
    Assignee: Canon Kabushiki Kaisha
    Inventors: Minoru Watanabe, Noriyuki Kaifu, Chiori Mochizuki
  • Patent number: 7095050
    Abstract: Monolithic, tandem, photonic cells include at least a first semiconductor layer and a second semiconductor layer, wherein each semiconductor layer includes an n-type region, a p-type region, and a given band-gap energy. Formed within each semiconductor layer is a sting of electrically connected photonic sub-cells. By carefully selecting the numbers of photonic sub-cells in the first and second layer photonic sub-cell string(s), and by carefully selecting the manner in which the sub-cells in a first and second layer photonic sub-cell string(s) are electrically connected, each of the first and second layer sub-cell strings may be made to achieve one or more substantially identical electrical characteristics.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: August 22, 2006
    Assignee: Midwest Research Institute
    Inventors: Mark W. Wanlass, Angelo Mascarenhas