Abstract: A high integration dynamic random access memory is provided by this invention. Furthermore, a write method is provided such that the cell size of two-and three-transistor gain cell memories is reduced. A dynamic memory incorporating a thin-channel transistor as the write element such that long data storage retention is achieved in the memory devices of this invention. A dynamic memory cell having low operating power and high density is also realized by this invention.

Abstract: An electron transfer device is implemented in a structure which is readily capable of achieving charge transfer cycle frequencies in the range of several hundred MHz or more and which can be formed by conventional semiconductor integrated circuit manufacturing processes. The device includes a substrate having a horizontal extent and a pillar on the substrate extending from the substrate vertically with respect to the horizontal extent of the substrate. The pillar is formed to vibrate laterally with respect to the vertical length of the pillar at a resonant frequency which can be several hundred MHz. Drain and source electrodes extend from the substrate vertically with respect to the horizontal extent of the substrate, and have innermost ends on opposite sides of the pillar. The pillar is free to vibrate laterally back and forth between the innermost ends of the drain and source electrodes to transfer charge between the electrodes.

Abstract: The high-gain photodetector is formed in a semiconductor-material body which houses a PN junction and a sensitive region that is doped with rare earths, for example erbium. The PN junction forms an acceleration and gain region separate from the sensitive region. The PN junction is reverse-biased and generates an extensive depletion region accommodating the sensitive region. Thereby, the incident photon having a frequency equal to the absorption frequency of the used rare earth crosses the PN junction, which is transparent to light, can be captured by an erbium ion in the sensitive region, so as to generate a primary electron, which is accelerated towards the PN junction by the electric field present, and can, in turn, generate secondary electrons by impact, according to an avalanche process. Thereby, a single photon can give rise to a cascade of electrons, thus considerably increasing detection efficiency.

Abstract: Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.

Abstract: According to the semiconductor thin-film and semiconductor device manufacturing method of the present invention, an insulating film having a through-hole between two layers of silicon film is provided, the silicon film is partially melted by irradiating a laser thereon, and a substantially monocrystalline film is continuously formed extending via the through-hole from at least part of the layer of silicon film below the insulating film that continues to the through-hole, to at least part of the layer of silicon film above the insulating film. It is therefore sufficient to form a through-hole with a larger diameter than that of a hole formed by the conventional method, because the diameter of the through-hole in the insulating film may be the same size or slightly smaller than the size of a single crystal grain that comprises the polycrystal formed in the silicon film below the insulating film. Costly precision exposure devices and etching devices are therefore unnecessary.

Abstract: A method and a BICMOS structure are provided. The BiCMOS structure includes an SOI substrate having a bottom Si-containing layer, a buried insulating layer located atop the bottom Si-containing layer, a top Si-containing layer atop the buried insulating layer and a sub-collector which is located in an upper surface of the bottom Si-containing layer. The sub-collector is in contact with a bottom surface of the buried insulating layer.

Abstract: The cellular structure of the power device includes a substrate that has a highly doped drain region. Over the substrate there is a more lightly doped epitaxial layer of the same doping. Above the epitaxial layer is a well region formed of an opposite type doping. Covering the wells is an upper source layer of the first conductivity type that is heavily doped. The trench structure includes a sidewall oxide or other suitable insulating material that covers the sidewalls of the trench. The bottom of the trench is filled with a doped polysilicon shield. An interlevel dielectric such as silicon nitride covers the shield. The gate region is formed by another layer of doped polysilicon. A second interlevel dielectric, typically borophosphosilicate glass (BPSG) covers the gate. In operation, current flows vertically between the source and the drain through a channel in the well when a suitable voltage is applied to the gate.

Abstract: A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD?V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD.

Abstract: A method for fabricating a thin film transistor (TFT) is described. A MoNb gate is formed on a substrate, and an insulating layer is formed on the substrate covering the gate. A channel layer is formed on the insulating layer above the gate, and a source/drain is formed on the channel layer to constitute a TFT. Since the gate is constituted of a MoNb layer, the contact resistance thereof can be reduced.

Abstract: A power module includes a power semiconductor device having a first terminal, a second terminal, and a third terminal. The second terminal is a control terminal to regulate flow of electricity between the first and third terminals. A gate driver has an output node coupled to the second terminal of the power device. The gate driver includes an upper transistor and a lower transistor provided in a half-bridge configuration. The output node of the gate driver is provided between the upper and lower transistors. A first delay circuit is coupled to a control terminal of the upper transistor to provide a first delay period for a first gate drive signal being applied to the control terminal of the upper transistor. A second delay circuit is coupled to a control terminal of the lower transistor to provide a second delay period for a second gate drive signal being applied to the control terminal the lower transistor. The first delay period is different from the second delay period.

Abstract: A high power semiconductor device including gate electrodes also includes an active region of an approximately rectangular shape, located on a semiconductor substrate; a drain electrode located on the active region; and first and second source electrodes which are disposed on opposite sides to the drain electrode so that the first and second source electrodes face each other across at least some of the gate electrodes. The directions of currents carried by the first and second source electrodes are opposite to each other.

Abstract: The invention encompasses a board-on-chip package comprising an insulative substrate having circuitry thereon and an opening therethrough. A semiconductive-material-comprising die is adhered to the substrate and electrically connected to the circuitry with a plurality of electrical interconnects extending through the opening. A metal foil is in physical contact with at least a portion of the die. The invention also encompasses a method of forming a plurality of board-on-chip packages. An insulative substrate is provided. Such substrate has a repeating circuitry pattern thereon, and a plurality of openings therethrough. The openings are in a one-to-one correspondence with individual of the repeated circuitry patterns. A plurality of semiconductive-material-comprising dies are adhered to the substrate. Circuitry supported by the dies is electrically connected with the circuitry on the substrate utilizing a plurality of electrical interconnects extending through the openings.

Abstract: A multiplexer structure includes a semiconductor substrate having a shared diffusion region. A first gate having a first finger and a second finger is disposed on the shared diffusion region, and a second gate having a first finger and a second finger is disposed on the shared diffusion region. A contact for a first input node is disposed on the shared diffusion region between the first and second fingers of the first gate, and a contact for a second input node is disposed on the shared diffusion region between the first and second fingers of the second gate. A contact for a collector node is disposed on the shared diffusion region between the first and second gates. In operation, closing the first gate electrically connects the first input node and the collector node, and closing the second gate electrically connects the second input node and the collector node.

Abstract: In a semiconductor device having a plurality of thin film transistors and matrix wiring lines formed on a substrate, the matrix wiring lines are electrically connected via resistors in order to prevent electrostatic destructions during a panel manufacture process and improve a manufacture yield.

Abstract: An integrated, tunable capacitance is specified in which the quality factor is improved by virtue of the fact that, instead of source/drain regions, provision is made of highly doped well terminal regions having a deep depth, for example formed as collector deep implantation regions. This reduces the series resistance of the tunable capacitance. The integrated, tunable capacitance can be used for example in integrated voltage-controlled oscillator circuits in which a high quality factor is demanded.

Abstract: There is provided a method by which lightly doped drain (LDD) regions can be formed easily and at good yields in source/drain regions in thin film transistors possessing gate electrodes covered with an oxide covering. A lightly doped drain (LDD) region is formed by introducing an impurity into an island-shaped silicon film in a self-aligning manner, with a gate electrode serving as a mask. First, low-concentration impurity regions are formed in the island-shaped silicon film by using rotation-tilt ion implantation to effect ion doping from an oblique direction relative to the substrate. Low-concentration impurity regions are also formed below the gate electrode at this time. After that, an impurity at a high concentration is introduced normally to the substrate, so forming high-concentration impurity regions. In the above process, a low-concentration impurity region remains below the gate electrode and constitutes a lightly doped drain region.

Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

Abstract: A photodetector for use with relatively thin (i.e., sub-micron) silicon optical waveguides formed in a silicon-on-insulator (SOI) structure comprises a layer of poly-germanium disposed to couple at least a portion of the optical signal propagating along the silicon optical waveguide. Tight confinement of the optical signal within the waveguide structure allows for efficient evanescent coupling into the poly-germanium detector. The silicon optical waveguide may comprise any desired geometry, with the poly-germanium detector formed to either cover a portion of the waveguide, or be butt-coupled to an end portion of the waveguide. When covering a portion of the waveguide, poly-germanium detector may comprise a “wrap-around” geometry to cover the side and top surfaces of the optical waveguide, with electrical contacts formed at opposing ends of the detector.

Abstract: In a nonvolatile memory cell, the floating gate (160) has an upward protruding portion. This portion can be formed as a spacer over a sidewall of the select gate (140). The spacer can be formed from a layer (160.2) deposited after the layer (160.1) which provides a lower portion of the floating gate. Alternatively, the upward protruding portion and the lower portion can be formed from the same layers or sub-layers all of which are present in both portions. The control gate (170) can be defined without photolithography. Other embodiments are also provided.

Abstract: A high density mask-type read only memory (ROM) device and a method of fabricating the high density mask-type read only memory (ROM) device using a salicide process. The method utilizes buried N+ bit lines, thick oxides for forming non-programmable cells, thin gate oxides in regions in which the thick field oxide has been removed to form programmable cells, polysilicon gate structures as word lines, and deposition of a single silicide layer. Since only one silicide layer is deposited, the manufacturing process requires less steps. The resultant ROM device has a silicide layer over the word lines and portions of the buried bit lines that serves to reduce word line and bit line resistance. This results in a ROM device with improved operational speed of the memory cells.