Abstract: In accordance with principles of the invention, there is provided an arbitration system for multiple requesters of a shared data transfer resource, such as a system bus or a peripheral bus. The disclosed system arbitrates among multiple classes of requesters which are divided into multiple levels of a request hierarchy. In the example embodiment, the multiple requesters include logic for processing received data from the network, logic for processing data to be transmitted onto the network, logic for moving transmit and receive descriptors between the host memory and the adapter, logic for reporting status from the adapter to the host, and logic for generating an error and maintenance status update from the adapter to the host. The new system ensures fairness between transmit and receive processes, that FIFOs associated with transmit queues are not underrun, and further that notification of non-error and maintenance status changes are processed with minimal latency.

Abstract: A network is monitored for reports indicative of a connection state among ports of a communications network. Certain ports are designated as being in a transition, and a transition table is created for each transition. The transition table includes locations that directly relate the connectivity of a first port with respect to a second port, as well as locations that relate the connectivity of other ports. The contents of the transition table are evaluated to determine the likely configuration of the communications network. State machines may be used to resolve conflicting data within the transition table, by providing a likely connection output based upon different entries within the transition table. A voting scheme is used to evaluate the outputs of the state machines and update the transition table when appropriate, and the updated transition table may also be evaluated.

Abstract: In a computer network, a method of random sampling of network packets is provided including the steps of providing a network switch, providing a monitoring device, the monitoring having a memory and a data storage unit, providing a network interface to connect the network switch to the monitoring switch, selecting a reference error check code value in the monitoring device, receiving a first network packet from the network switch, comparing, in the network monitoring device, the reference error check code with an error check code of a first network packet, storing the first network packet in the monitoring device if the error check code value of the first network packet matches the reference error check code of the first network packet, and repeating the steps of receiving, comparing and storing for subsequent network packets.

Abstract: Disclosed herein is a carrier for removeably interconnecting a memory storage device having a SCSI ID and a controller ID with an equipment frame. The carrier holds the memory storage device. The carrier removeably attaches to the equipment frame to facilitate hot swappability of the memory storage device. The carrier has a base, a facial assembly with a display and a circuit assembly. The base removeably locks into the equipment frame and supports a memory storage device and the facial assembly. The circuit assembly electrically connects the memory storage device and the display. Accordingly, the display can display information relating to the memory storage device including SCSI ID and controller ID.

Abstract: A method and apparatus for combining writes and avoiding redundant writes are disclosed. Based on values such as overhead message size, largest message size, packet round trip time, cache block size, dirty cache region size and separation, channel throughput, and the identity of cached data values, a write region containing cached data is selected and (if non-empty) is written across the network. Depending on conditions, the selected write region includes either two dirty regions and an intervening clean region or only one dirty region. In the latter case, the other dirty region is flushed by a subsequent write operation. The goals of avoiding network congestion, updating the cache promptly, and utilizing available network bandwidth are balanced according to conditions in the cache and on the network.

Abstract: A method and apparatus for replacing data in a list of buffers is provided. The list of buffers has a hot end and a cold end. The buffers at the hot end are maintained in a FIFO list and the buffers at the cold end are maintained in an LRU list. Requested data is located and, if the requested data is located in the LRU portion of the buffer list, the buffer containing the requested data is moved to the head of the FIFO list. If the data is located in a buffer in the FIFO portion of the buffer list, no rearrangement is required. If the requested data is not located in the buffer list, the data is stored into the buffer at the tail end of the LRU list, then the buffer is moved to the head of the FIFO list.

Abstract: Editing the parameters for several network devices coupled to a computer network can be a cumbersome task. To simplify the task, a method of editing parameter settings for more than one network device using a graphical user interface is introduced. First, a set of network devices is displayed on a display screen. Then, a user selects a set of network devices to edit parameters for. Next, a list of parameters for the selected network devices is displayed on a display screen. The parameters that have the same value for all the selected network devices are displayed on the screen. However, parameters that do not have the same value for all the selected network devices are not displayed on the screen. Instead, the field is usually left blank. A user can edit the parameter settings displayed on the screen. When a parameter modification is approved, the modified parameter value is sent to all the selected network devices.

Abstract: The present invention relates to a system and method for implementing peripheral device bus mastering in a mobile computer system. The system uses the mobile computer system's microcontroller for programming a DMA controller, generating and sending command signals, and receiving completion status after transfer of data is complete. The micro-controller accesses a data buffer descriptor list. The data buffer descriptor list describes each data transfer that the micro-controller initiates, controls, and completes. The Direct Memory Access controller which is programmed by the micro-controller transfers data to and from a memory section of the mobile computer system. A bus controller is used for implementing a memory data transfer request from the DMA controller means and the micro-controller means.

Abstract: When a portable recording medium is judged to have been loaded in a peripheral device, a microprocessor of the peripheral device checks whether the portable recording medium is a recording medium bearing update data for use updating a program to be executed by the micro-processor. If the portable recording medium is a recording medium bearing update data for updating such a program, the update data is read from the portable recording medium and the program is updated in accordance with the read update data. If, however, the portable recording medium is not a recording medium bearing update data for updating a the program, the recording medium is ejected from the peripheral device. The program in the peripheral device can thus be updated even if the peripheral device is not connected to a host computer.

Abstract: This invention makes it possible for a customer computer to connect to an online service provider computer by phone, Internet, or other method, pay a fee to said service provider, and obtain additional processing and storage resources for the customer's computer. The resources can take the form of virtual storage and processing capabilities. These capabilities give the customer computer what appears to be additional local processing power and/or additional local storage, this storage possibly including preloaded software and/or data.The additional resources made available to the customer computer can be used either to enhance the customers' local needs (such as access to virtual storage for additional disk space, or access to a more powerful processor of similar type for program execution), or these additional resources can be used by the customer computer to support services on-line that otherwise would be unavailable, impractical, or unaffordable.

Abstract: Data storage apparatus comprises: a memory having a plurality of addressable memory locations for storage of data items and memory address input means for receiving addresses of locations to be accessed; main input means for receiving an input address corresponding to a memory location; a counter for changing a count in response to a clock signal; address adjustment means for combining the count with an input address to generate an adjusted address corresponding to a memory location and supplying the adjusted address to the memory address input means; and means for accessing the memory location at the address supplied to the memory address input means. Also provided is a data storage method, and data processing systems including the data storage systems.

Abstract: A rate based mechanism for determining which data to replace in a cache when the cache is full. The computer system processes data, which are associated with multiple channels or processes. These channels or processes have different, cyclic rates. When the cache is full, the system chooses the data to replace by selecting the data block in the cache that has the lowest rate and is the most recently used.

Abstract: A DMA controller which responds without operating system intervention to virtual addresses provided by application programs, and a memory management unit for providing translations between physical addresses of input/output devices and addresses on a system input/output bus for data transferred by the DMA controller.

Abstract: A method and system within a data processing system are disclosed for receiving information from a communications network. The data processing system includes a communications adapter, having an adapter memory, and a host memory. The communications adapter is coupled to the communications network, which transmits information to the data processing system in packets including a packet header and packet data. According to the present invention, a portion of a packet of information is received from the communications network at the adapter memory within the communications adapter. The portion of the packet of information includes at least a packet header that specifies a length of the packet of information and a destination address within the host memory. In response to receipt of the portion of the packet of information, a transfer of the packet of information from the adapter memory to the host memory is prepared prior to receipt of a final portion of the packet of information at the adapter memory.

Abstract: A cache memory for a computer uses content-addressable tag-compare arrays (CAM) to determine if a match occurs. The cache memory is partitioned in four subarrays, i.e., interleaved, providing a wide cache line (word lines) but shallow depth (bit lines). The cache can be accessed by multiple addresses, producing multiple data outputs in a given cycle. Two effective addresses and one real address are applied at one time, and if addresses are matched in different subarrays, or two on the same line in a single subarray, then multiple access is permitted. The two content-addressable memories, or CAMs, are used to select a cache line, and in parallel with this, arbitration logic in each subarray selects a word line (cache line).

Abstract: A method and apparatus are provided for maintaining a N-way associative directory utilizing a content addressable memory (CAM). A congruence class from the N-way associative directory including a directory entry identified for a data operation is read into the CAM for the data operation. The directory entry for the data operation in the CAM is locked while the data operation is pending. Other entries in the congruence class are available. When the data operation is completed, checking for a state change is performed. Responsive to an identified state change, the directory entry for the data operation in the CAM is updated or marked as changed. The congruence class including the updated directory entry is marked as dirty. In accordance with features of the invention, the changed congruence class directory entries in the CAM are accumulated and scheduled to be written back to the N-way associative directory.

Abstract: In a method and apparatus for selective convolutional interleaving or de-interleaving of symbols or data bits, a plurality of segments are defined in random access memory, with each segment including a different number of locations for storing symbols. Previously stored symbols are sequentially read out of current locations in the segments respectively, and new symbols are read into the current locations. Next locations in the segments are redesignated as current locations respectively, and the operation is repeated until all of the symbols have been interleaved or de-interleaved. The first location in each segment is designated by a respective segment pointer. The current and next locations are designated as relative offset pointers from the segment pointers, and these locations are incremented by incrementing the offset pointers. Interleaving or de-interleaving operation is determined by the direction in which the segments are sequentially selected for the read/write operations.

Abstract: Two data storage systems are interconnected by a data link for remote mirroring of data. Each volume of data is configured as local, primary in a remotely mirrored volume pair, or secondary in a remotely mirrored volume pair. Normally, a host computer directly accesses either a local or a primary volume, and data written to a primary volume is automatically sent over the link to a corresponding secondary volume. Each remotely mirrored volume pair can operate in a selected synchronization mode including synchronous, semi-synchronous, adaptive copy - remote write pending, and adaptive copy - disk. Direct write access to a secondary volume is denied if a "sync required" attribute is set for the volume and the volume is not synchronized. If a "volume domino" mode is enabled for a remotely mirrored volume pair, access to a volume of the pair is denied when the other volume is inaccessible.

Abstract: An arbitration bus is arranged between a core logic chip set and a plurality of peripheral devices in order to arbitrate requests by the peripheral devices to use system memory of a computer system. Three or two arbitration signals carried on the arbitration bus. Means are provided to differentiate two levels of priority in each peripheral device. The core logic chip set can make a response pressing or otherwise so as to promote the overall performance. Preemption is provided so that peripheral devices can be overridden without wasting time when it is necessary to do so. Each peripheral device outputs a row address strobe (RAS) signal, all of which are connected together to form a open-collector signal to the core logic chip set for automatically accessing corresponding memory banks of system memory.

Abstract: A semiconductor disk device comprising a flash memory having a plurality of blocks, each block constructed of a block information memory area for storing the number of erase cycles of the block, a plurality of data memory areas for storing data, and a logical sector address memory area associated with each of the data memory areas for storing a logical sector address, an address conversion table for converting the logical sector address into a physical block number, and a CPU which converts the logical sector address (LSA) into the physical block number (PBN) according to the address conversion table. The CPU also searches the latest data memory area in the physical block in the flash memory based on the logical sector address and reads the content of the latest data memory area. Thus, a small-capacity address conversion table for memory management results.