Abstract: A multiprocessor data processing system having store-through first-level caches with separate instruction and operand sections and a store-in second-level cache that is shared between the processors and which has separate instruction and operand sections. Dual second-level caches, each mappable to all of shared memory, enhance cache performance. The second-level cache memory space is divided into a plurality of segments, with each segment having a dedicated instruction tag memory, a dedicated operand tag memory, a dedicated instruction cache memory, and a dedicated operand cache memory. The segments may be addressed in parallel to further enhance cache performance.

Abstract: A computer system for protecting memory comprising a processor having address outputs and executing a stored program, a memory having a control input, an address-decoder for providing a control signal to the control input of the memory in response to associated address outputs from the processor, and a window circuit. The window circuit comprises a range detector responsive to the address outputs for generating a range-detection signal indicative of an address from the processor being within a protected range, the protected range non-identical to the entirety of the space of addresses within the memory. Access to memory locations within the protected range is permitted only if a request signal is received from the processor. If the request signal is asserted for an unexpectedly long time an error condition is annunciated, for example the processor is reset.

Abstract: A data processing device includes a data processing core (43), a cache (33) connected to the core and having a cache width, and a bus (31) for receiving from an information source external to the data processing device a burst of information having a width which exceeds the cache width by a width difference. The cache is coupled to the bus to receive and store a first portion of the burst which is equal in width to the cache width. A storage circuit (35) is coupled to the bus to receive and store a second portion of the burst corresponding to the width difference, and the storage circuit has an output coupled to the core.

Abstract: The power consumed by a cache memory when the cache is read is reduced by utilizing a cache access circuit to prevent the cache from being read when the information stored in the cache is invalid, such as when the processor is powered up, reset by a user, or an invalidation bit is set.

Abstract: The personal computer hard disk protection system is designed to protect data stored on computer hard disks of computers utilizing non-ISA buses while permitting multiple user operation. The personal computer hard disk protection system prevents unauthorized access to the hard disk by software applications, and permits safe servicing of requests which use the BIOS. The basis for the personal computer hard disk protection system functions is the dynamic transformation of the file system to the configuration of the current user. The system is based on a hardware device called the protection-program support module and a set of protection programs, most of which is stored in the protection-program support module. The protection program support module is an external board and is connected to the computer system bus and to the base IDE connection level, the latter of which is controlled by the protection program support module for either permitting or denying access to the hard disk.

Abstract: A RAID disk array that is adaptable to host I/O traffic, wherein the RAID configuration is hidden from the host computer. The system dynamically determines the RAID configuration used to store host data to maximize response time performance and minimize the loss of disk space used for data protection. To maximize response time and avoid a write penalty, small write operations are mapped into RAID 1 configurations, and medium and large write operations are mapped into RAID 3 configurations. These segments are migrated into RAID 5 configurations as a background operation, to minimize the disk space lost. The system hides configuration changes necessary for the addition and/or deletion of disks to the disk array. While these changes are in progress, the disk array remains on-line and all host data is available for access and modification.

Abstract: A buffer having a predetermined number, M, of input ports adapted for connection to one of a plurality of devices. The devices have different numbers, P, of ports, where P is less than, or equal to, M. The buffer includes a processor for determining the number of ports, P, of the one of the plurality of devices connected to the M ports of the buffer. The buffer couples the P ports of the device to M output ports of the buffer in a ratio of [M/P] sequences. A method for determining the number, P, of transmit/receive ports of one of a plurality of devices. After connecting one of the plurality of devices to the buffer, a predetermined pattern of data is placed on each of the output ports when the connected device is in a loopback mode. The pattern of data is detected at the input ports in response to the predetermined data placed on the output ports. The predetermined pattern on the output ports is compared with the detected pattern to determine the number of ports, P, of the connected one of the devices.

Abstract: In order to allow prefetching of pointer-type data structure, an instruction word of load instruction has pointer hints indicating that the data being loaded by the instruction comprises a pointer specifying the address of the next data. When a CPU executes such an instruction, and the data requested by that instruction is loaded from a main memory, a prefetch circuit in a memory interface circuit uses this pointer to read a block containing the data specified by this pointer from the main memory, then stores temporarily in a prefetch buffer provided therein. When CPU executes a load instruction requesting reading of the data specified by this pointer, the data in this stored block is supplied to CPU through a processor interface circuit and a cache control circuit.

Abstract: A memory circuit, method of access, and method of preparation of data, which enable construction of a redundancy-free memory and hardware of a smaller circuit size, wherein of the data (C2, C6, -C2, -C2, -C6, C6, and C2) of a redundancy-ridden read only memory in which the same first data is stored a plurality of addresses, the same data existing at a plurality of addresses are assigned to a single address of the read only memory so as to prepare and record at predetermined addresses the data (C2, C6, -C6, and -C2) of the read only memory, provision is made of an address conversion circuit comprised of a decoder, two-input OR circuits for transforming the single address data of the read only memory to accessible addresses without requiring advance change of the address designations when there are address designations, and the single address of the memory is accessed and data output in accordance with the address designation.

Abstract: Logic circuitry and a corresponding method for computing an indexed set address utilized by a cache to mitigate the probability of a conflict miss occurring for a given memory access. Implemented at component or system level, the logic circuitry performs pseudo-random indexing of a set address obtained from a memory address during a memory access by a processor unit. This is accomplished by performing operations consistent with modulo operations on the memory address.

Abstract: A multiprocessor computer system has data processors and a main memory coupled to a system controller. Each data processor has a cache memory. Each cache memory has a cache controller with two ports for receiving access requests. A first port receives access requests from the associated data processor and a second port receives access requests from the system controller. All cache memory access requests include an address value; access requests from the system controller also include a mode flag. A comparator in the cache controller processes the address value in each access request and generates a hit/miss signal indicating whether the data block corresponding to the address value is stored in the cache memory.

Abstract: A plurality of setting data stored in a serial register 11 and externally supplied replacement data are inputted into selectors 12. Either of the setting or replacement data is provided to the respective one of the setting inputs S.sub.1 -S.sub.n in a digital signal processing unit 10. Each of the selectors 12 usually selects the setting data. When a selector 12 is specified by a decoder 13 based on address data, it only selects the replacement data. When the replacement and address data are suitably set, the computation condition of the digital signal processing unit 10 can be partially changed without rewriting of the setting data in the serial register 11.

Abstract: To provide an optical disk recorder capable of reading data currently recorded even if the power supply is turned off during the recording of record data in a system using an optical disk in which table-of-contents information is not recorded in an area other than a user's recording area for recording record data and recording and reproducing of data is controlled according to the table-of-contents information.

Abstract: A method for updating mass storage device configuration records during a configuration change within a computer system is disclosed. A unit configuration record is stored in a system mass storage device. The unit configuration record is unique to each system and it includes a configuration identification, a sequence number and an alteration count table. In addition, a logical device identifier is stored in each mass storage unit within the system. The logical device identifier is unique to each mass storage device unit and it includes a configuration identification, a unit number and an alteration count. If a configuration update is necessary, the corresponding alteration count of the unit configuration record is first incremented, a new logical device identifier is then built with the new alteration count, and finally the new logical device identifier is written to a mass storage device that requires update.

Abstract: To change the priority order of a DMA transfer circuit and a CPU for the bus use right in a data processing system comprising the DMA transfer circuit, when an overflow occurs in the DMA transfer timer during DMA transfer, a request signal for shifting the bus use right from the DMA transfer circuit to the CPU is outputted to a bus use right decision circuit to suspend DMA transfer. After the bus use right is transferred from the DMA transfer circuit to the CPU, the CPU resumes operation. When an overflow occurs in the DMA transfer timer, a request signal for shifting the bus use right from the CPU to the DMA transfer circuit is outputted to the bus use right decision circuit to transfer the bus use right from the CPU to the DMA transfer circuit with the same means as the start of DMA transfer and to resume DMA transfer.

Abstract: A controller for a synchronous DRAM is provided for maximizing throughput of memory requests to the synchronous DRAM. The controller maintains the spacing between the commands to conform with the specifications for the synchronous DRAMs while preventing gaps from occurring in the data slots to the synchronous DRAM. Furthermore, the controller allows memory requests and commands to be issued out of order so that the throughput may be maximized by overlapping required operations which do not specifically involve data transfer. To achieve this maximized throughput, memory requests are tagged for indicating a sending order. Thereafter, the memory requests may be arbitrated when conflicting memory requests are queued and this arbitration process is then decoded for simultaneously updating scheduling constraints. The memory requests may be further qualified based on the scheduling constraints and a command stack of memory request is then developed for modifying update queues.

Abstract: A memory device includes an array of memory cells that are arranged in rows and columns. A row address latch connected to the address bus stores a row address on the address bus during a precharge period responsive to a transition of a row address strobe from an active low state to an inactive high state. A row decoder connected to the row address latch decodes the stored row address, and a redundancy checker determines if the decoded row is defective and, if so, selects a redundant row of memory cells for addressing. The row address decoder and the redundancy checker perform these respective functions during the precharge period. The memory device also includes a wordline controller that fires a wordline corresponding to the addressed row responsive to a transition of the row address strobe from its inactive high state to its active low state.

Abstract: The invention provides an exclusive control unit among computers which can reliably perform an exclusive control for a shared resource while keeping a system running as a whole even if a problem occurs in any of the computers in the system. Each of the computers is connected to the others through a LAN and to a distributed shared memory bus for connecting each distributed shared memory card mounted on each computer with the others.

Abstract: A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.

Abstract: A memory control device and method receives a request to transfer a series of first-unit K byte (for example, 512) data in an address space, divides the first-unit K into second-unit L (for example, 64), assigns priority levels to the second-unit L, issues plural times a data transfer instruction to transfer the L-byte data to a memory device comprising a plurality of memories operable in a consecutive access mode, and thus accesses memories in response to the request to transfer the K-byte data. The L-byte data are sequentially allocated in third units S (for example, 64) specified by the data transfer instruction to the memories. The third unit is equal to L or is obtained by dividing L, and is a multiple of an activation unit of the memories. The S-byte data are accessed in the allocated memories in the consecutive access mode.