Abstract: A method of using a computer to analyze an extended finite state machine model of a system includes receiving at least one requirement expression, determining at least one path of states and transitions through the model, evaluating at least one of the requirement expressions based on at least one of the determined paths through the model to determine whether the path satisfies the requirement expression, and generating a report based on the evaluating.

Abstract: The present invention relates to electronic packaging and a method for manufacturing the same. According to an embodiment of the present invention, an emulator chip package is designed and assembled such that a bottom portion of the emulator chip package is approximately the same electronic package used to package the target chip. Additionally, a top portion of the emulator chip package is approximately a slightly modified version of the same type of package used to package the target chip. According to an embodiment of the present invention, the top portion of the emulator chip package is attached to the bottom portion of the emulator chip package. The lead connector pins of the top portion of the package preferably leads up, while the connector pins of the bottom portion of the package preferably leads down.

Abstract: The present invention relates to a method of modelling a circuit travelled by a drilling mud during drilling, the circuit including both the well and the surface equipment, in particular solid separation devices, in which method, for each time sequence, there are calculated the mass concentration of each liquid and solid species present in the mud, the total flow rate, and the grain size distribution of each solid species downstream from each item of equipment. The invention also provides inversion of the above method to estimate the size of the cuttings on the basis of the measured efficiency of solid separation devices.

Abstract: Spinal modeling is based on a concept called spinal energy which assumes that the spine assumes a shape to minimize spinal energy. Spinal energy depends on parameters called stiffness coefficients. These parameters can be determined from human data which, by hypothesis, are universal for a large class of humans. The method adapts Newton's method to the manifold SO(3)n to find a solution of model of the human spine. Where basins of attraction are small in Newton's method, homotopy methods are introduced to move from known solutions to unknown solutions. By setting the gradient of the spinal energy to zero, Newton's method is used to solve the inverse problem of finding stiffness coefficients from human data. A new approach to improving deformed spines uses the modeling method based on spinal energy. This approach preserves maximally the range of motion of the spine. The technique used is vertebraplasty; i.e.

Abstract: A method of data compression for continuous or piecewise linear curves in two variables is presented which can guarantee that any compression error is exclusively on one selected side of the curve. Limiting errors to one side is required when simulating integrated circuit performance to determine if a design will have speed-related problems. In such a simulation it is necessary to calculate both the minimum and maximum possible time delays for a logic chain of circuit elements. Data compression of the transistor or gate voltage versus time relationship is necessary to reduce the very large amount of data that is required for the simulation. Data compression may introduce errors into the data in either direction. If it is necessary to have any possible error confined to one side of the curve, the compressed data must be shifted toward the desired error side by at least the maximum possible data error.

Abstract: A method of optimized design of an HVAC air-handling assembly for a climate control system on a vehicle includes the steps of generating a basic design of the HVAC air-handling assembly and analyzing a performance of the basic design of the HVAC air-handling assembly using an engineering analytical technique. The method also includes the steps of varying the basic design of the HVAC air-handling assembly based on the performance analysis and using the optimized basic design of the HVAC air-handling assembly in generating the HVAC air-handling assembly design.

Abstract: In a music synthesis system, a scanning apparatus repeatedly scans a physical attribute of a vibrating object at a sequence of points of the vibrating object so as to repeatedly generate corresponding sequences of values. The music synthesis system generates an audio frequency waveform whose shape corresponds to the sequences of values. The vibrating object may be a physical object or a simulated object. The system may include a sensor for receiving user input, and means for mapping the user input into a stimulus signal that is applied to the vibrating object. In a preferred embodiment, the object vibrates and is manipulated by the user at haptic frequencies (0 to 15 hertz), while the sequences of scanned values are cyclically read at an audio frequencies so as to generate an audio frequency waveform whose timbre varies at the haptic frequencies associated with the object's vibration.

Abstract: A computer implemented method which does not require a stored dictionary for correcting spelling errors in a sequence of words comprises storing a plurality of spelling rules defined as regular expressions for matching a potentially illegal n-gram which may comprise less than all letters in the word and for replacing an illegal n-gram with a legal n-gram to return a corrected word, submitting a word from said sequence of words to the spelling rules and replacing a word in the string of words with a corrected word.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: A method for efficiently changing the embedded processor type in verification of system-on-chip (SOC) integrated circuit designs containing embedded processors. The verification software is used to generate and apply test cases to stimulate components of a SOC design (“cores”) in simulation; the results are observed and used to de-bug the design. Typically, the embedded processor type changes as SOC designs change. However, changing the processor type may cause errors in verification due to the presence of processor-specific code distributed throughout the verification software. Thus, changing the processor type can entail a substantial re-write of the verification software. In the method according to the present invention, in verification software for verifying a SOC design including an embedded processor, processor-specific code is localized in a processor driver.

Abstract: In accordance with methods and systems consistent with the present invention, an improved fact recognition system is provided that automatically learns from syntactic language examples and semantic language examples, thus facilitating development of the system. The language examples are rather simplistic and can be provided by a lay person with little training, thus relieving the need for knowledge engineers. Furthermore, the learning performed by the improved fact recognition system results in a collection of probabilities that is used by the system to recognize facts in a typically more accurate manner than conventional systems.

Abstract: Method and apparatus for detecting and analyzing effects of noise in a digital circuit that arises from a coupling of signals produced by switching of a first gate and a second gate in a timed relationship. Where each of a first gate and a second gate can switch within a selected switching time interval, the gate switching effects are combined and the second gate output signal is analyzed with reference to the first gate input signal. Otherwise, the gate switching effects are not combined. When the second gate output signal satisfies at least one of three criteria, this condition is interpreted as indicating that the second gate permits propagation of a noise pulse produced at the first gate.

Abstract: Methods and apparatus for generating a hierarchical representation of a circuit include obtaining a netlist corresponding to the circuit, the circuit including a plurality of subcircuits. A hierarchical representation of the circuit is then generated from the netlist, the hierarchical representation including the plurality of subcircuits arranged among a plurality of levels of the hierarchical representation. Each one of the plurality of subcircuits has an associated subcircuit definition. In addition, each of a plurality of subsets of the subcircuits share a same subcircuit definition, where memory storage for the same subcircuit definition is shared by the subcircuits in each of the subsets. Moreover, each one of the plurality of subcircuits has a dynamic voltage state.

Abstract: A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.

Abstract: The wiring design software 3 reads in design information, analyzes it to generate a wiring problem and correlates bonding pads and pins of a semiconductor package to each other (S102, S104). The wiring design software 3 then searches a wiring route while permitting crossing by using the Dijkstra method and the like, calculates an evaluation value by weighting the length of a candidate route with a coefficient W when the candidate route crosses a monitoring side E, and selects a candidate route having a minimum evaluation value as a partial route (S110).