Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable.

Abstract: Provided are a method, system, and article of manufacture, wherein a determination is made that a first data array in a plurality of data arrays has to be repaired to replace a failed storage device within the first data array. A storage device is selected from a selected data array of the plurality of data arrays to replace the failed storage device, wherein a data value corresponding to the selected data array is less than the data value corresponding to the first data array.

Abstract: A method and apparatus to achieve a resource optimized, class of Reed Solomon decoders, featuring balanced pipelined stages and parallel algorithmic components. The Reed Solomon decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for Reed Solomon decoders, and can lead to reduced buffering, resulting in significant hardware savings.

Abstract: An integrated circuit device includes a plurality of memory circuits, a memory hibernation state control circuit to bring the memory circuits into a hibernation state in response to an external command, a state controller which indicates an interrupt in a memory circuit in a hibernation state, and a plurality of partial error checking and correcting (ECC) code generating circuits which are provided for the memory circuits, respectively, to code hold data of an address of a memory circuit in a hibernation state in accordance with a rule of a Hamming code determinant by an interrupt in the memory circuit in the hibernation state. The integrated circuit device further includes a code storage memory which obtains ECC code data corresponding to all of the hold data based on partial ECC codes coded by the partial ECC code generating circuit and stores the ECC code data in a corresponding address.

Abstract: An iterative decoding device for a communication receiver includes a decoder for decoding received encoded data blocks by a next iteration initialization, a controller to choose one of the first and second hard decision bits in order for the validity of a CRC field, associated to this received data block, to be checked, and a first memory. The controller, when the CRC field of a block is invalid, orders the decoder to store the final stakes associated to the block in the first memory to require the transmission of a redundant version of the block, and when the redundant version is received, to initialize the decoder with the stored final stakes before it applies the next iteration initialization mechanism to the received redundant version.

Abstract: A system and method are provided for efficiently initializing a redundant array of independent disks (RAID). The method monitors host write operations and uses that information to select the optimal method to perform a parity reconstruction operation. The bins to which data access write operations have not occurred can be initialized using a zeroing process. In one aspect, the method identifies drives in the RAID array capable of receiving a ‘WriteRepeatedly’ command and leverages that capability to eliminate the need for the RAID disk array controller to provide initialization data for all disk array initialization transfers. This reduces the RAID array controller processor and I/O bandwidth required to initialize the array and further reduces the time to initialize a RAID array. In a different aspect, a method is provided for efficiently selecting a host write process for optimal data redundancy and performance in a RAID array.

Abstract: A decoder is configured to include an acquisition-unit configured to acquire first respective likelihoods of data-bits and second respective likelihoods of parity-bits. The data-bits and the parity-bits are included in code data obtained by LDPC-encoding the data-bits with a low density parity check matrix. The decoder also includes a detecting-unit configured to detect reliabilities of the first respective likelihoods and the second respective likelihoods. The decoder also includes a forming-unit configured to form an update schedule representing an order of updating the first and second respective likelihoods in order of increasing reliability, in accordance with the reliabilities. The decoder also includes an updating-unit configured to update the first and second respective likelihoods in the order represented by the update schedule, with the low density parity check matrix. The decoder also includes a discriminating-unit configured to execute hard decision of the likelihoods updated by the updating-unit.

Abstract: A method for performing Viterbi decoding using a reduced trellis memory is provided that includes dividing a block of data into a plurality of segments. A feed-forward process is performed on each of the segments to generate a trellis for each of the segments. A traceback process is performed on each of a plurality of overlapping segment pairs, each segment pair comprising a first segment and a second segment, to generate a traceback result for the first segment and a traceback result for the second segment. The traceback result for the second segment is discarded to generate a decoder output based on the traceback result for the first segment.

Abstract: Provided is a method, apparatus and computer program product for detecting a transport format of a multiplexed transport channel used for transferring binary data. A path metric value is determined, which estimates likelihood for a hypothetical trellis path to end at a predetermined state, for every state of a trellis stage of a possible end bit position of a data block of the transport channel. Then, for each possible end bit position a number of path metric values which indicate higher likelihood for the hypothetical trellis path to end at said predetermined state than an initial state is calculated, and the best end bit positions which lead to highest values of the calculated number are selected and error checking is performed for the selected best end bit positions to detect the transport format. The proposed selection of best end bit positions leads to a reduced number of decoding operations.

Abstract: Systems and methods for data loss protection are presented. In one embodiment, a data loss protection switch includes a first port, a second port, an error threshold management component and a multiplexer. Components of the data loss protection switch cooperatively operate to efficiently protect data. The first port receives information from a first data stream. The second port receives data from a second data stream. The error threshold management component analyzes errors in the first data stream and the second data stream. The multiplexer is controlled by the error threshold management component and selects among the first and second data streams based on the analysis.

Abstract: Embodiments of the present invention provide multi-level signal memory with LDPC and interleaving. Thus, various embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder to LDPC code data values to be written into the memory cells and an interleaver adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values. Other embodiments may be described and claimed.

Abstract: The correction of errors in the transport and processing of qubits makes use of logical qubits made up of a plurality of physical qubits. The process takes place on a spatial array of physical qubit sites arranged with a quasi-2-dimensional topology having a first line of physical qubit sites and second line of physical qubit sites, where the first and second lines are arranged in parallel, with the sites of the first line in registration with corresponding sites in the second line. Between the first and second lines of physical qubit sites are a plurality of logic function gates, each comprised of a first physical qubit gate site associated with a first physical qubit site in the first line, and a second physical qubit gate site associated with the physical qubit site in the second line that corresponds to the first physical qubit site.

Abstract: A method of operating an integrated circuit which includes an input module, an output module, and a processing module coupled to the input module and the output module. The method includes, in the input module, receiving a first data segment; in the processing module, reading a hard coded identifier from an identifier module coupled to the processing module, processing the first data segment with the hard coded identifier to generate a first encoded data segment; and in the output module, transferring the first encoded data segment for storage on a storage system.

Abstract: Identifying a burst error is disclosed. Identifying includes computing a syndrome check polynomial corresponding to a burst of length up to 2t?1 in received data and identifying a shortest burst based on the longest consecutive root sequence of the syndrome check polynomial. The received data is corrected based at least in part on the shortest burst.

Abstract: A packet transmission apparatus is provided. The packet transmission apparatus transmits a packet having a limited arrival deadline through a best-effort network. The packet transmission apparatus includes an automatic packet retransmission section to control retransmission of an undelivered packet, a forward error correction coding section to add a redundant packet to a data packet block, and a redundancy determining section to dynamically determine redundancy of the redundant packet based on observed network state information, so that a loss rate after error correction at a receiver achieved by only the retransmission of the undelivered packet satisfies an allowable loss rate after error correction.

Abstract: Various embodiments implement distributed block coding (DBC). DBC can be used for, among other things, distributed forward error correction (DFEC) of source data in communication systems or parity backup for error correction of source data in storage systems where the source data may be corrupted by burst errors. A distributed block encoder (DBE) encodes sequential source data symbols with a plurality of sequential block encoders to produce interleaved parity codewords. The interleaved parity codewords enable decoding of error-corrected source data symbols with a distributed block decoder (DBD) that utilizes a plurality of sequential block decoders to produce the error-corrected source data symbols. A distributed register block encoder (DRBE) and a distributed register block decoder (DRBD) can each be implemented in a single block encoder and a single block decoder, respectively, by using a distributed register arrangement.

Abstract: A maximum a posteriori detector includes a single state metric engine that performs forward and backward processing to produce forward and backward state metrics. The state metric engine includes a plurality of processes that each perform both the forward and the backward processing operations. The system further includes memory that stores the forward and backward state metrics that are produced by the engine in appropriate orders for the forward and backward processing. A number of multiplexers provide the appropriate branch metrics and apriori values to adder strings in each of the processors in accordance with an associate decoding trellis.

Abstract: In one embodiment, the present invention includes a method for receiving incoming data in a processor and performing a checksum operation on the incoming data in the processor pursuant to a user-level instruction for the checksum operation. For example, a cyclic redundancy checksum may be computed in the processor itself responsive to the user-level instruction. Other embodiments are described and claimed.

Abstract: The present invention provides an LDPC encoder, a channel encoder of a portable internet system including the LDPC encoder, and an encoding method thereof. The LDPC encoder according to the present invention generates a Costas array, shifts it, generates an analogous circulation parity check matrix having a repeated pattern from the shifted Costas array, and performs encoding by using the parity check matrix. With this LDPC encoder, complexity of encoding system may be reduced.

Abstract: A method and apparatus for transmitting a broadcast physical layer packet in a mobile communication system supporting multi-slot transmission and hybrid Automatic Repeat Request (H-ARQ) are provided. The method comprises initially transmitting the broadcast physical layer packet according to a fixed transmission format for at least one first slot interval and retransmitting the broadcast physical layer packet for at least one second slot interval using a variable transmission format different from the transmission format used in the first slot interval.