Abstract: A system (and method) for a recovery of data from a lost sector in a storage system, which includes a set of readable and lost sectors in a plurality of disks in the storage system, includes identifying a lost sector of at least one disk of the storage system, determining whether the data from the lost sector is capable of being recovered, and, if the data from the lost sector is capable of being recovered, generating a recovery formula for the lost sector and recovering the data from the lost sector based on the recovery formula.

Abstract: An apparatus and method to generate a dual transport stream. The apparatus includes an eraser encoder to receive a turbo stream and to eraser-encode the turbo stream, a duplicator to provide a parity insertion region for the eraser-encoded turbo stream, and a multiplexer to receive a normal stream and to multiplex the turbo stream processed by the duplicator and the normal stream to generate the dual transport stream. The duplicator provides the parity insertion region using a ½-rate conversion method or ¼-rate conversion method. Only the turbo stream is detected prior to the transmission of the dual transport stream, and the parity is inserted into the parity insertion region, so that the turbo stream can be robustly processed.

Abstract: Herein described is a system and a method of detecting and correcting data bit errors using a sequence of one or more codewords transmitted through a communication channel without intersymbol interference. Each of the one or more codewords incorporates or encodes one or more parity bits. The codewords are processed by a Non-ISI Meta-Viterbi detector that utilizes a Meta-Viterbi algorithm. The Non-ISI Meta-Viterbi detector comprises an event weight processor, a computational circuitry, a parity syndrome calculator, and an error correction circuitry. The Non-ISI Meta-Viterbi detector receives an output generated from a symbol detector and processes the received output using a trellis having 2t states. In a representative embodiment, the overall implementation complexity of the Non-ISI Meta-Viterbi detector is bounded by no more than ?+(?)2t2t operations, wherein t represents the number of parity bits used in a codeword and ? represents codeword length in bits.

Abstract: A path metric difference computation unit is disclosed for computing path differences through a multiple-step trellis. Path differences are computed between paths through a multiple-step trellis, wherein a first path is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period.

Abstract: Systems and methods are provided for encoding a stream of datawords based on a tensor product code to provide a stream of codewords, and detecting and decoding a stream of received data based on a tensor product code to provide a decoded stream of data. In one aspect, the tensor product code is based on two codes including an inner code and an outer parity hiding code, where the outer parity hiding code is an iterative code. In certain embodiments, the outer parity hiding code is a Turbo code or a low density parity check (LDPC) code.

Abstract: An add-compare-select (ACS) unit generates first path metrics having a first bit-pair and a most significant bit-pair (MSB) each including a high bit and a low bit. A first ACS circuit produces the first bit-pair and a first carry. A limiting circuit generates the MSB based on the first carry, and limits the MSB to a first predetermined value. A MSB maximum select (MS) unit receives an MSB of second path metrics from another ACS unit, and compares the MSBs of the first and the second path metrics to determine MSB decision signals based on maximum likelihood selection. A MSB storage unit stores the MSB of the first path metrics. A reset unit resets the high bit of the MSB of the first path metrics to a second predetermined value when the high bits of the MSBs of the first and the second path metrics reach the first predetermined value.

Abstract: A memory system including asymmetric high-speed differential memory interconnect includes one or more buffer units coupled to one or more memory units such as memory modules, for example, via a parallel interconnect. The memory system also includes a memory controller coupled to each of the buffer units via a respective serial interconnect. The memory controller may control data transfer between the memory controller and the one or more buffer units. During normal operation, each of the buffer units may be configured to receive data from the memory controller via the respective serial interconnect and to transmit the data to the one or more memory units via the parallel interconnect, in response to receiving command information from the memory controller. Further, the memory controller may be configured to modify a phase alignment of information transmitted from the memory controller based upon information received from the buffer units.

Abstract: A method is provided of data storage by encoding a bit stream on a surface. The method involves printing coded data on the surface which encodes the bit stream, and printing alignment data on the surface which is indicative of a position of the coded data on the surface. The alignment data has a first registration structure indicative of a plurality of reference points indicative of a position of the coded data in an alignment direction, and a second registration structure indicative of a plurality of reference points indicative of a position of the coded data in a direction perpendicular to the alignment direction.

Abstract: There are provided a content data transmission method, device, and program that minimize serious disturbances in reproduced content on the reception side, caused by a transmission error of encoded data, without sending feedback information from the reception side to the transmission side. When an encoder creates encoded data to be distributed, the encoder creates plural items of encoded data at the same time or creates FEC data at the same time in advance and, when storing the data in a file, stores the data as if the data were one item of encoded data. When a distribution server distributes the data using the file, the plurality of items of encoded data are automatically distributed at the same time and the FEC data is distributed. A client receives the plurality of items of encoded data or the FEC data to reduce the probability of data shortage due to a packet loss and, as a result, the deterioration in the image quality and the audio quality is reduced.

Abstract: A method for the iterative decoding of a block of bits having a number N of bits to be decoded where N is a whole number greater than or equal to two, using an iterative decoding algorithm, comprises the generation of a current block of N intermediate decision bits by executing an iteration of the decoding algorithm, followed by the verification of a stability criterion for the current block by comparison of the current block with a given block of N reference bits. If the stability criterion is satisfied, the iterations of the iterative decoding algorithm are stopped and the current block of intermediate decision bits is delivered as a block of hard decision bits. Otherwise another iteration of the decoding algorithm is executed.

Abstract: An ID (identification) information, user data, and a control information are disposed each in one block, and subject to an error correction code (ECC). The user data and control information are disposed in an ECC block 1, while the ID information is disposed in an ECC block 2. The ECC blocks 1 and 2 are coded separately for error correction. The blocks thus coded for error correction are disposed in one physical structure, data is modulated, a sync signal is added to the modulated data, and then the data is written to an optical disc having the above data format.

Abstract: Data bits to be encoded are split into a plurality of subgroups. Each subgroup is encoded separately to generate a corresponding codeword. Selected subsets are removed from the corresponding codewords, leaving behind shortened codewords, and are many-to-one transformed to condensed bits. The final codeword is a combination of the shortened codewords and the condensed bits. A representation of the final codeword is decoded by being partitioned to a selected subset and a plurality of remaining subsets. Each remaining subset is decoded separately. If one of the decodings fails, the remaining subset whose decoding failed is decoded at least in part according to the selected subset. If the encoding and decoding are systematic then the selected subsets are of parity bits.

Abstract: Methods and apparatus are provided for more efficiently computing error checking codes such as cyclic redundancy checks (CRCs). Based on particular characteristics of CRCs, an input sequence is intelligently divided into a series of subsequences. Each subsequence gets selected bits from the input sequence. The error checking code is calculated on each subsequence. The results are bit-interleaved and an error checking code is calculated over this interleaved result to obtain the error checking code over the entire sequence.

Abstract: A DTV transmitting system includes a first pre-processor for coding first enhanced data having a high priority for forward error correction (FEC) at a first coding rate and expanding the first enhanced data at a first expansion rate, and a second pre-processor for coding second enhanced data having a low priority for FEC at a second coding rate and expanding the second enhanced data at a second expansion rate. The receiving system further includes a data formatter for generating enhanced data packets, a multiplexer for multiplexing the enhanced data packets with main data packets, an RS encoder for RS-coding the multiplexed data packets, and a data interleaver for interleaving the RS-coded data packets and outputting a group of interleaved data packets having a head, a body, and a tail.

Abstract: This invention provides a processor for writing data contained in payload data of a data packet to memory. The processor may, in some embodiments, be a central processing unit of a memory tag. The processor does not include a write buffer. The processor may comprise a first register adapted to latch first data corresponding to a segment of the payload data; and a second register adapted to receive second data from the payload data to enable the validity of the data latched into the first register to be established before data is written to memory. A memory device, a method for writing data contained in payload data, a data packet, a method of writing data into a non-volatile memory and a memory tag may also be provided.

Abstract: To control a decoding latency, larger blocks are nonequally segmented into smaller ones. The decoding process starts directly after reception of the first small block. The latency is defined by the latency of the last small block decoding. Changing the number of iterations during the turbo-code decoding also permits control of the decoding latency.

Abstract: A method of transmitting data through a link comprises encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital data in a serializer, generating test data in a pseudo-random binary sequence generator circuit, transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation, and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation. The encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated chip. The test data includes data to generate colors in a visual image, and the encoded and serial digital data is received, deserialized, decoded, and displayed in a display unit.

Abstract: To specify defect management information to be used in a short time in an information recording medium having a defect information area capable of recording plural sets of defect management information and a selection information area capable of recording plural sets of selection information for selecting a set of defect management information from the defect information area. The selection information includes information about a position where the latest management information at the time of writing is written, and history information indicating that the selection information is updated.

Abstract: A method of preparing data for transmission. The method includes providing a block of data, generating a plurality of first dimension code words including first dimension forward error correction FEC elements, the elements of each code word may be used interchangeably to reconstruct a data portion of the block corresponding to the code word, defining a plurality of second dimension source words formed of the generated elements and generating for at least two of the defined second dimension source words, different numbers of parity elements.

Abstract: In a transmitting entity a message of a first time period L is divided into N self-decodable blocks and transmitted towards a communications network. At the communications network the N self-decodable blocks are detected by a receiving entity and decoded on a block basis.