Abstract: Provided is an interleaving method that can reduce error occurring during transmission at a receiving end in an Orthogonal Frequency Division Multiplexing (OFDM) system. According to the interleaving method, transmitted data bits are recorded in an interleaving memory; and the stored data bits are read based on a predetermined sequence to perform symbol interleaving, tone interleaving and cyclic shift simultaneously. Also, to simplify the logic of the OFDM system, the data bits transmitted from an interleaver go through Fast Fourier Transform (FFT) mapping, and the FFT mapped data bits are modulated. In short, the logic can be simplified by performing FFT mapping followed by modulation.

Abstract: The present invention relates to an inter-sequence permutation (ISP) encoder. The ISP encoder comprises: a receiving means to receive an information bit sequence input; a first outputting means for outputting a first code bit output; a second outputting means for outputting a second code bit sequence output; a bit-adding means coupled to the receiving means, the bit-adding means processing the received information bit sequence input prior to any subsequent processing in the ISP encoder; a first convolutional code encoder coupled between the bit-adding means and the first outputting means; a second convolutional code encoder; and an inter-sequence permutation interleaver coupled between the bit-adding means and the second convolutional code encoder. The second convolutional code encoder is coupled between the inter-sequence permutational interleaver and the second outputting means.

Abstract: A detector for detecting information carried by a signal having a sawtooth-like shape. The detector includes a first band-pass filter with center frequency around a first frequency value for filtering the signal and generating a first filtered signal, a second band-pass filter with center frequency around a second frequency value for filtering the signal and generating a second filtered signal, a first comparator for comparing the first filtered signal with a reference level and generating a first compared signal, a second comparator for comparing the second filtered signal with the reference level and generating a second compared signal, a clock generator for generating a reference clock having a frequency close to the first frequency value according to the second compared signal, and a detection module for generating a bit signal representing the information according to the first compared signal and the reference clock.

Abstract: A virtual display driver that can be dynamically loaded and unloaded for remote control of a host computing system. The host computing system includes an original display driver that updates an output display of the computing system based on display commands. A remote control executive executes in kernel-mode within an operating environment provided by the computing system and dynamically loads and unloads the virtual display driver as requested by a user. The remote control executive inserts hooks within the functions provided by the original display driver to trap the display commands received by the original display driver and direct the commands to the virtual display driver for communication to a remote client computer.

Abstract: A novel technique for combining deinterleaving operation with Fast Fourier Transformer (FFT) modules and other post FFT modules in a receiver to reduce processing time. In one example embodiment, the deinterleaving operation, in the post FFT module, is combined with FFT and demapper operations to reduce the processing time and complexity.

Abstract: In a method for error correction of packet data, in particular DAB (digital audio broadcasting) data packets, code words being used over multiple data packets, redundancy information for error correction is added while maintaining the original packet data structure, at the cost of a free data field or a useful data field. The cycle of the error protection is selected as a multiple of a minimum size for a packet length.

Abstract: Methods and associated structures for improved erasure correction and detection in digital communication channels utilizing modified Reed-Solomon decoding of encoded digital data. Methods and associated apparatus in accordance with features and aspects hereof perform Galois Field element generation in descending order for Reed-Solomon erasure detection and correction. Real time computation of Galois Field elements in descending order as required for erasure detection and correction features and aspects hereof eliminates the need for costly, complex, large, high speed lookup tables as previously practiced in the art for storing Galois Field element values pre-computed in the same ascending order of reception of the encoded code words. Features and aspects hereof may thus be applied in digital read channel applications including, for example, digital telecommunications receive/read channels and digital data storage read channels.

Abstract: To provide a constitution capable of reducing production cost in a semiconductor device for display of a type integrally formed with a drive circuit with a digital signal as an input signal and a pixel matrix unit, a signal dividing circuit is formed on a substrate where drive circuits and a pixel matrix unit are to be formed simultaneously with the drive circuits and the pixel matrix unit in view of fabrication steps by which fabrication steps of the signal dividing circuit per se and steps required for connecting the signal dividing circuit to wirings on the substrate can be dispensed with without adding further steps.

Abstract: A method for reducing the computational complexity of a Viterbi decoder, which is suitable for all code rates of a convolutional code applied by the Viterbi decoder. The method dramatically reduces the branch metric computation to thus reduce the complexity of implementing the Viterbi decoder, without affecting the capability of error correction. Upon the best mode, the Viterbi decoder can reduce the required branch metric computation to ¼k of the original computation.

Abstract: Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bit according to a code characterized by a parity check matrix (H matrix) to generate a sequence of encoded bits, wherein the H matrix is capable of being expressed as H=[Hp|Hd]=[S|J*P*T], S being a dual-diagonal matrix, J being a single parity check matrix, P being an interleaver permutation matrix, and T being a repeat block matrix, wherein the H matrix is a column permuted version of an original H matrix, wherein clashes associated with an interleaver corresponding to the P matrix are reduced by adopting the H matrix instead of the original H matrix, and outputting the sequence of encoded bits.

Abstract: One set of syndromes is calculated from a first data string from among a plurality thereof including at least 2t+1 pieces of symbols as a parity string, and coefficients of an error locator polynomial from the one set of the syndromes. Whether or not a correction is successful is judged by using the coefficients of the error locator polynomial and the same calculation is performed for a second data string if a correction failure is judged. Contrarily, if a correction success is judged, an error of the first data string is corrected by using the aforementioned set of the syndromes and the coefficients of the error locator polynomial.

Abstract: An encoder in a data transmission/reception system has a byte interleaver for performing folding interleaving on encoded data ED in units of a byte and a packet interleaver for performing folding interleaving, in units of a packet, on byte interleave data BID generated by this byte interleaver. A decoder has a packet de-interleaver for performing folding de-interleaving, in units of a packet, on packet interleave data PID' and a byte de-interleaver for performing folding de-interleaving, in units of a byte, on byte interleave data BID' generated by this packet de-interleaver. It is thus possible to correct a significant burst error containing a packet loss even with an error correction code having a very small code length.

Abstract: In an error control apparatus on a receiving side using a hybrid ARQ which combines an error correcting encoding method and an automatic repeat request method, a buffer stores hard decision result data or soft output data instead of soft decision information in order to reduce a memory capacity of the buffer, and re-encodes the data stored to be provided to a combiner. Alternatively, the number of bits of the data stored in the buffer is restricted or a memory included in a decoder is used as an HARQ buffer.

Abstract: A memory device includes a main memory cell array and a redundant memory cell array configured to store a first parity code for data stored in the main memory cell array. The device further includes a parity generator configured to generate a second parity code responsive to reading of the stored data from the main memory cell array, and a comparator configured to compare the first and second parity codes. In some embodiments, the parity generator configured to generate the second parity code during a copyback operation.

Abstract: A wideband code division multiple access (W-CDMA) user equipment (UE) operating in frequency division duplex mode for receiving data over at least one of a plurality of high speed (HS) shared control channels (SCCHs) is disclosed. The UE includes means for monitoring the plurality of HS-SCCHs; means for receiving a packet over at least one of the plurality of HS-SCCHs; and means for determining whether a UE identification is present in the packet and whether a circular redundancy code (CRC) of the packet is correct by processing a mask field. The mask field has an N-bit CRC modulo 2 combined with an N-bit UE identification.

Abstract: A data recorder includes a first memory element including read/write capability, a second memory element including non-volatile memory and a controller for realizing memory management functions. The controller responds to a predetermined triggering event by writing selected data from the first memory element to the second memory element. The selected data include data units that have been modified after a prior triggering event.

Abstract: For the transmission of information with verification of transmission errors, a useful information message (M) is transmitted in a determined frame while being associated with a determined number p of transmission error verification bits (CRC,S) also transmitted in the frame. In order to have an element allowing the verification of intentional errors, determined number p1 of the transmission error verification bits form a seal (S) obtained from a determined sealing function, where p1 is a number less than p. Application to radiocommunications equipment requiring the verification of the integrity and the authentication of the messages transmitted.

Abstract: A disk controller includes a determining unit for determining whether check codes added to data read from a disk drive are first type check codes or second type check codes, and a check code conversion unit. The check code conversion unit includes conversion unit for converting, if the check codes added to the read data are first type check codes, the first type check codes into second type check codes and a writing unit for writing the data provided with the second type check codes into the disk drive. The disk controller also includes a control unit for performing background processing, which is performed at a time different from processing performed when a data read request or a data write request is sent from a host device, by reading data provided with check codes from the disk drive and by starting check code conversion processing performed by the check code conversion unit.

Abstract: A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32 K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.

Abstract: Embodiments of a method and apparatus for a transceiver decoding an Ethernet signal. The method includes receiving an Ethernet bit stream. The bit stream is at least one of low-complexity decoded by a low-complexity decoder of the transceiver or high-complexity decoded by a high-complexity decoder of the transceiver. If the bit stream fails a low-complexity decoding test, then the bit stream is high-complexity decoded. The low-complexity decoding and high complexity decoding are iteratively repeated until the bit stream passes the low-complexity decoding test.