Patents Examined by G. Fourson
  • Patent number: 5358877
    Abstract: A method for electrically isolating an integrated circuit element in an acoustic charge transport device comprises the steps of providing a semi-insulating substrate; providing an epitaxial layer with a thickness and carrier concentration appropriate for an ACT device; providing a circuit element semiconductor layer in the epitaxial layer for construction of an integrated circuit element, the layer having a thickness substantially less than the thickness of the epitaxial layer and having a carrier concentration substantially greater than the ACT epitaxial layer; laterally isolating the semiconductor layer from other regions of the ACT epitaxial layer; and bombarding the semiconductor layer with protons at a dose sufficient to provide significant vertical electrical isolation from underlying regions of the epitaxial layer semi-insulating with minimal detrimental effect on the electrical characteristics of the semiconductor layer.
    Type: Grant
    Filed: March 29, 1991
    Date of Patent: October 25, 1994
    Assignee: Electronic Decisions Inc.
    Inventors: Michael J. Hoskins, Martin J. Brophy
  • Patent number: 5252511
    Abstract: An isolation method in a semiconductor device which includes the steps of growing a pad oxide layer on a semiconductor substrate, depositing a polysilicon layer and a first silicon nitride layer on the pad oxide layer, removing and patterning the first silicon nitride layer to define an active region and a field region, depositing a second silicon nitride layer and a thick oxide layer, forming oxide spacers and nitride spacers, ion-implanting impurities, removing the oxide spacers, growing a field oxide layer, and sequentially removing the first silicon nitride layer, the nitride spacers, the polysilicon layer, and the pad oxide layer. This method minimizes the bird's beaks regions and increases the effective isolation distance of the device.
    Type: Grant
    Filed: January 17, 1992
    Date of Patent: October 12, 1993
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Cheon-su Bhan, Yun-gi Kim, Byeong-yeol Kim
  • Patent number: 5248350
    Abstract: A process for forming field oxide regions between active regions in a semiconductor substrate. Pad oxide, polysilicon and first silicon nitride layers are successively formed over substrate active regions. The first nitride layer, polysilicon layer, pad oxide layer and a portion of the substrate are then selectively etched to define field oxide regions with substantially vertical sidewalls. A second silicon nitride is provided on the substantially vertical sidewalls, and field oxide is grown in the field oxide regions. The first silicon nitride, polysilicon and pad oxide layers are then removed. The presence of the polysilicon layer prevents the formation of a sharp corner between the field oxide and active regions if an overetch occurs during the removal of the pad oxide layer.
    Type: Grant
    Filed: November 30, 1990
    Date of Patent: September 28, 1993
    Assignee: NCR Corporation
    Inventor: Steven S. Lee
  • Patent number: 5229306
    Abstract: A method for gettering metal atoms (28) from a subsequently contaminated silicon substrate (12) is disclosed. A smoothed or polished first surface (16) has a thin germanium silicon layer (20) deposited thereon. A silicon layer (24) is deposited onto the germanium silicon layer (20) to seal the layer (20) between the substrate (12) and the silicon layer (24). Electronic components (26) are fabricated on a second surface (14) of the silicon substrate (12) which causes the metal atoms (28) to contaminate the substrate as a result of contamination in normal processing (12). As the substrate (12) is heated during normal processing of the devices, metal atoms (28) in the substrate of a result of contamination, diffuse in the substrate (12) to the misfit dislocations at the germanium-silicon (20)/silicon interface.
    Type: Grant
    Filed: December 27, 1989
    Date of Patent: July 20, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Keith J. Lindberg, Greg Gopffarth, Jerry D. Smith
  • Patent number: 5215934
    Abstract: A method by which the gate oxide in an EEPROM device is selectively thickened over the channel region nearest to the drain so as to penalize erase-type behavior during programming of a selected cell. First the lattice structure in a portion of the channel near said drain region is intentionally damaged to enhance subsequent thermal oxidation therein. Next, the channel is thermally oxidized to form the tunnel oxide for the device. Due to the damage inflicted in the portion of the channel near the drain, the tunnel oxide over the damaged region is thicker relative to the other portion of the channel. A thicker gate oxide near the drain thwarts drain disturbance in adjacent memory cells while speeding up source erase performance.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: June 1, 1993
    Inventor: Jyh-Cherng J. Tzeng
  • Patent number: 5192708
    Abstract: A method of providing sublayer contacts in vertical walled trenches is proposed. In accordance with the present invention, the phosphorus doped amorphous silicon is deposited at temperatures less than 570.degree. C. The conversion into the extremely large crystal low resistivity polysilicon is accomplished by a low temperature anneal at 400.degree. C. to 500.degree. C. for several hours and a short rapid thermal anneal (RTA) treatment at a high temperature approximately 850.degree. C. for twenty seconds. These two conversion heat treatments are done at sufficiently low thermal budget to prevent any significant dopant movement within a shallow junction transistor. After anneal, the excess low resistivity silicon is planarized away by known techniques such as chemical/mechanical polishing.
    Type: Grant
    Filed: April 29, 1991
    Date of Patent: March 9, 1993
    Assignee: International Business Machines Corporation
    Inventors: Klaus Beyer, Edward C. Fredericks, Louis L. Hsu, David E. Kotecki, Christopher C. Parks
  • Patent number: 5192706
    Abstract: This is a method of forming a semiconductor integrated circuit with isolation regions, (possibly wide and narrow) comprising of a thin oxide film and deposited anisotropic oxide. It uses an inorganic layer (e.g. noncrystalline silicon) to mask what will be active areas and allows for the growth of a thermal oxide film in the trenches reducing the parasitic channel formation along the trenches. The use of anisotropic oxide to fill the trenches allows for wide and narrow trenches to be simultaneously filled to the desired depth. The removing of inorganic layer and the use of anisotropic oxide to fill the trenches produces a flat planar surface and finer isolation regions.
    Type: Grant
    Filed: August 30, 1990
    Date of Patent: March 9, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Mark S. Rodder
  • Patent number: 5185271
    Abstract: In a method of manufacturing a raster transfer image sensor, the charge transport channels and the channel-bounding regions and the vertical anti-blooming channels are formed in a self-registering manner in that the channel-bounding regions are provided via a mask, and the intervening charge transport channels are provided in a maskless doping step. Since this doping is also carried out in the channel-bounding regions, a doping profile favorable for the photosensitivity is obtained in the channel-bounding regions with a maximum concentration at a distance from the surface.
    Type: Grant
    Filed: March 25, 1991
    Date of Patent: February 9, 1993
    Assignee: U.S. Philips Corp.
    Inventor: Jacobus G. C. Bakker
  • Patent number: 5180871
    Abstract: A process for producing a phenol from the steps of:(a) partially hydrogenating a benzene, followed by separating the reaction mixture into respective components of a cyclohexene, a cyclohexane and a benzene;(b) oxidizing or hydrating the separated a cyclohexene into oxygen-containing compounds of a cyclohexane;(c) dehydrogenating the oxygen-containing compounds of a cyclohexane into a phenol;(d) dehydrogenating the cyclohexane separated in step (a) to convert the cyclohexane into a benzene; and(e) returning a part or all of hydrogen formed in steps (c) and (d) back to step (a).
    Type: Grant
    Filed: February 24, 1992
    Date of Patent: January 19, 1993
    Assignee: Mitsui Petrochemical Industries, Ltd.
    Inventors: Fujihisa Matsunaga, Hiroshi Fukuhara, Mitsuki Yasuhara
  • Patent number: 5175122
    Abstract: A method of planarizing the surface of a silicon wafer of the type employing trench isolation is disclosed where the trenches and active areas of wafer surface may be of varying widths. The trenches and active areas are covered with a conformal coating of silicon oxide, and, according to one embodiment, this coating is subjected to an etch to leave sidewall spacers of oxide at the sidewalls of the trenches, then a second conformal coating of oxide is applied. A first layer of photoresist is applied to the face and patterned to leave photoresist only in the wider trenches. According to another embodiment the remaining photoresist of the first layer is reflowed by a heat treatment to account for any misalignment or the like. A second layer of photoresist is applied, then etched back to the conformal coating on the active areas, leaving some resist in narrow trenches.
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: December 29, 1992
    Assignee: Digital Equipment Corporation
    Inventors: Ching-Tai S. Wang, Gregory J. Grula
  • Patent number: 5173444
    Abstract: A method for forming a semiconductor device isolation region including steps of forming a first silicon oxide film on a silicon substrate, depositing a first silicon nitride film over the first silicon oxide film, and removing the first silicon oxide film and first silicon nitride film in a device isolation region by using a resist pattern, which is formed by a one-time photolithographic step, as a mask so as to expose the surface of the silicon substrate, removing the resist pattern, and oxidizing the exposed surface of the silicon substrate so as to form a second silicon oxide film having a smaller thickness than the first silicon oxide film and to deposit a second silicon nitride film, removing the second silicon nitride film by anisotropic etching until the second silicon oxide film is exposed in the device isolation region so as to make the second silicon nitride film remain as the side wall portion of the silicon nitride film in only the opening side wall portion of the first silicon nitride film, etchi
    Type: Grant
    Filed: September 16, 1991
    Date of Patent: December 22, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Akio Kawamura
  • Patent number: 5173446
    Abstract: A semiconductor substrate comprises a foundation, a semiconductor monocrystalline film formed on the foundation, and a high-melting-point metal film or a high-melting-point metal alloy film disposed in at least part of a region between the semiconductor monocrystalline film and the foundation. The high-melting-point metal film disposed below the semiconductor monocrystalline film can be utilized as a conductor in a semiconductor device.
    Type: Grant
    Filed: June 13, 1991
    Date of Patent: December 22, 1992
    Assignee: Ricoh Company, Ltd.
    Inventors: Toshifumi Asakawa, Daisuke Kosaka, Haruo Nakayama
  • Patent number: 5173439
    Abstract: A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrate. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.
    Type: Grant
    Filed: April 2, 1991
    Date of Patent: December 22, 1992
    Assignee: International Business Machines Corporation
    Inventors: Somanath Dash, Michael L. Kerbaugh, Charles W. Koburger, III, Brian J. Machesney, Nitin B. Parekh
  • Patent number: 5171702
    Abstract: A BiCMOS structure and a method for making the same is disclosed, where the dielectric layer between the emitter electrode and the base region is formed of a deposited dielectric. After definition of the bipolar and MOS moat regions, a layer of polysilicon is deposited thereover, and removed from the bipolar region. The base implant is performed either prior to or after the etch of the polysilicon layer. A layer of TEOS oxide is formed thereover and is etched to remain in portions of the bipolar region, with an emitter contact formed therethrough and a portion of the bipolar region exposed at which the extrinsic base is formed. An alternative embodiment of the invention includes scaling the emitter contact by forming sidewall oxide filaments therewithin. A second layer of polysilicon is disposed thereover to form the emitter electrode, and to merge with the first layer to form the gates of the MOS transistors.
    Type: Grant
    Filed: October 29, 1991
    Date of Patent: December 15, 1992
    Assignee: Texas Instruments Incorporated
    Inventors: Scott H. Prengle, Robert H. Eklund
  • Patent number: 5169408
    Abstract: A wafer processing apparatus including a head defining an etching chamber, the sidewall of the head being slidable along the base so that the sidewall and base will normally define an etch chamber; and the sidewall may be moved upwardly to open a discharge passage for rinsing water, and a deflecting surface for deflecting the rinsing water downwardly and draining the rinsing water from the passage. The housing is separable above the deflector ring to provide access to the wafer for inserting the wafer and replacing it.
    Type: Grant
    Filed: January 26, 1990
    Date of Patent: December 8, 1992
    Assignee: FSI International, Inc.
    Inventors: Rex L. Biggerstaff, Charles W. Skinner, Daniel J. Syverson, Mark L. Jenson, James G. Kegley
  • Patent number: 5166100
    Abstract: An ultragrating is a nanometer-period optical grating that is fabricated from a horizontal superlattice. A superlattice is a material structure grown on a substrate by molecular-beam epitaxy or metal-organic chemical vapor deposition and having periodic compositional variations. A horizontal superlattice is one in which the compositional variations are in a direction parallel to the substrate surface. By the selective removal of one of the superlattice materials, an ultragrating is obtained. The smallest grating periods possible before this discovery were those made by electron-beam lithographic techniques which are limited to values greater than 100 nanometers. Thus, the ultragrating with grating periods ranging from one to a hundred nanometers represents an order of magnitude advancement in the state of the art of making optical gratings. The ultragrating will fine utility in the design of advanced electronic devices and for general scientific and engineering purposes.
    Type: Grant
    Filed: December 6, 1990
    Date of Patent: November 24, 1992
    Inventors: Arthur C. Gossard, Paul K. Hansma, Scott A. Chalmers, Albrecht L. Weisenhorn
  • Patent number: 5166092
    Abstract: A method of growing compound semiconductor epitaxial layer by an atomic layer epitaxy, comprises the steps of blowing on a predetermined surface a compound source material gas constituted by atoms having an ion polarity different from atoms constituting the predetermined surface so that the compound source material is adsorped on the predetermined surface in a non-decomposed state, and decomposing the adsorped compound source material on the predetermined surface into atoms constituting crystals at the predetermined surface so as to grow an atomic layer of atoms having the same ion polarity as the compound source material gas. The ion polarity of the atomic layer prevents adsorption of the compound source material after the atomic layer is grown.
    Type: Grant
    Filed: October 30, 1990
    Date of Patent: November 24, 1992
    Assignee: Fujitsu Limited
    Inventors: Kouji Mochizuki, Nobuyuki Ohtsuka, Masashi Ozeki
  • Patent number: 5164338
    Abstract: The invention relates to a method of manufacturing a polycrystalline semiconductor resistance layer of silicon on a silicon body. First an insulating layer is formed on the silicon body and then a polycrystalline silicon layer is deposited. To the deposited polycrystalline silicon layer is applied a further polycrystalline silicon layer having a crystallite structure coarser with respect to that of the first polycrystalline silicon layer. The two polycrystalline silicon layers are additionally doped.
    Type: Grant
    Filed: October 24, 1990
    Date of Patent: November 17, 1992
    Assignee: U.S. Philips Corporation
    Inventors: Volker Graeger, Rolf U. D. Kobs, Horst Schafer, Heinrich Zeile
  • Patent number: 5164017
    Abstract: A method for cleaning reactors for the gas-phase processing of workpieces, particularly in the field of semiconductor technology and more particularly in the field of coating semiconductor substrates by means of chemical deposition processes, with less effort entails providing the reactor with a gas permeable inner wall within the usual gas impermeable outer wall, the inner wall surrounding a chamber for coating a workpiece by means of a chemical deposition process, plenums being formed between the inner and outer walls, and further with conduit means communicating between the exterior of the reactor and the plenums and conduit means communicating between the exterior of the reactor and the inner chamber, and effecting a cleaning cycle in which an etching gas is conducted through the inner chamber by being introduced into the reactor through one of the aforementioned conduit means and withdrawn from the reactor through another of the aforementioned conduit means.
    Type: Grant
    Filed: April 19, 1991
    Date of Patent: November 17, 1992
    Inventors: Rainer Moller, Dietmar Resch, Lutz Fabian
  • Patent number: 5164071
    Abstract: An improvement in iso-olefin production without substantial decrease in overall yield is obtained in an integrated process combining a fluidized catalytic cracking reaction and a fluidized catalyst olefin interconversion reaction when crystalline medium pore shape selective zeolite catalyst particles are withdrawn in partially deactivated form from the interconversion reaction stage and added as part of the active catalyst in the FCC reaction.
    Type: Grant
    Filed: February 28, 1991
    Date of Patent: November 17, 1992
    Assignee: Mobil Oil Corporation
    Inventor: Mohsen N. Harandi