Abstract: First, second, third and fourth impurity regions are formed on a major surface of a semiconductor substrate with prescribed spaces, to define first, second and third channel regions in portions held between the same. A select gate is formed on the first channel region through an insulating film, to define a transistor with the first and second impurity regions. A part of a control gate is formed on the third channel region through an insulating film, to define a transistor with the third and fourth impurity regions. A floating gate is formed on the second channel region and parts of the select gate and the control gate through an insulating film, to define a transistor with the second and third impurity regions. Both end portions of the floating gate are inwardly separated from upper positions of respective outer ends of parts of the select gate and the control gate, in order to improve an effect of shielding the floating gate against a fourth impurity region.

Abstract: In a method for manufacturing a semiconductor device using a LOCOS technique, a selective oxidation is performed using an oxidation-resistance film as a mask to form an element isolating oxide film on the semiconductor substrate. An inserting portion of the oxide film is formed under an end portion of the oxidation-resistance film. The feature of this method lies in that the inserting portion of the oxide film is left as an element isolating oxide film and the other portion thereof is removed to selectively expose the substrate, and then a monocrystalline silicon layer is formed on the exposed portion of the substrate and used as an element region.

Abstract: Disclosed is a method of making a semiconductor device that exemplarily comprises depositing a Ti/Pt layer onto a AuBe intermediate layer on a p-doped region of a semiconductor body. It also comprises depositing a Ti/Pt layer onto a n-doped region of the semiconductor body, or onto a AuGe intermediate layer on the n-doped region, followed by rapid thermal processing. Exemplarily, the device is a semiconductor laser, the n-doped region is InP, the p-doped region is InGaAs or InGaAsP, and RTP involves heating in the range 425.degree.-500.degree. C. for 10-100 seconds. The method comprises fewer processing steps than typical prior art methods, reduces the danger of fabrication error and of wafer breakage and, significantly, results in contacts that can be relatively thermally stable and can have very low specific contact resistance (exemplarily as low as 10.sup.-7 .OMEGA..multidot.cm.sup.2).

Abstract: A process for forming air-filled isolation trenches in a semiconductor substrate by a conformal chemical vapor deposition (CVD) of a silicon dioxide layer over the passivated surface of the semiconductor substrate in which intersecting trenches have been formed and partially filled with a material that can subsequentially be removed from under the CVD silicon dioxide layer, such materials include water soluble glasses and polymeric materials, such as a polyimide. The CVD silicon dioxide is etched back to the passivated surface of the semiconductor substrate, forming openings in the layer at the trench intersections that extend to the trench fill material. The fill material is removed through these openings. A CVD silicon dioxide layer is deposited to fill the openings, leaving a silicon dioxide cap bridging the air-filled trench. Water soluble glasses that may be used to fill the trench include BSG glass (B.sub.2 O.sub.3 content greater than 55%) and germanosilicate glass (GeO.sub.2 content greater than 50%).

Abstract: The disclosure relates to a method of forming in situ phosphorous doped polysilicon wherein a surface upon which phosphorous doped polysilicon is to be deposited is placed in a vacuum furnace and, after low pressure HCl cleaning of the surface and furnace, a predetermined ratio of silane and a gaseous phosphorous containing compound taken from the class consisting of phosphorous trichloride, tertiary butyl phosphine, isobutyl phosphine, trimethyl phosphate and tetramethyl phosphate are simultaneously passed through the furnace at predetermined pressure and temperature to provide a uniformly phosphorous doped layer of polysilicon on the surface.

Abstract: An ion-implantation method for implanting desired impurities selectively in a solid material is provided that comprises forming a blocking film on the solid material, and implanting the impurities in the solid material with the blocking film used as a shielding mask for ion implantation, wherein the blocking film is formed to have a gentle slope at its edge portions.

Abstract: A method of manufacturing an TGFET is described. The gate electrode comprises Mo, Ti, W, MOSi.sub.2, WSi.sub.2, TiSi.sub.2 or mixtures thereof formed on a photo-CVD nitride layer.

Abstract: Group VIB metal sulfide slurry catalysts having a pore volume in the pore size range 10 to 300.ANG. radius of at least 0.1 cc/g. Also, Group VIB metal sulfide catalysts having a surface area of at least 20 m.sup.2 /g. Suitable Group VIB metals are molybdenum and tungsten, preferably molybdenum. The Group VIB metal sulfide can be approximately a Group VIB metal disulfide. The slurry catalyst can be promoted with a Group VIII metal, such as nickel or cobalt.

Abstract: An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

Abstract: Here is disclosed an improved polysilicon pad LOCOS method. An underlying oxide film is formed on a main surface of a semiconductor substrate. Over the underlying oxide film, polysilicon to be a field oxide film is then deposited. Subsequently, a nitride film is formed on the polysilicon. Thereafter, the nitride film is patterned to leave patterns of a predetermined configuration in an area to be a device region. Using the patterned nitride film as a mask, the polysilicon other than a portion beneath the mask is thermally oxidized to form a field oxide film on the main surface of the semiconductor substrate. The nitride film having served as a mask is then removed to expose the unoxidized polysilicon remaining under the mask. Subsequently, the unoxidized polysilicon is etched away under predetermined conditions which do not allow any etching of the underlying oxide film.

Abstract: A process including forming peaks and valleys in a bonding surface of a first wafer so that the peaks are at the scribe lines which define dice. The peaks and not the valleys of the first wafer is bonded to a bonding surface of a second wafer. The device forming steps are performed on one of the wafers. Finally, the wafer in which the devices are formed is cut through at the peaks to form the dice. The peaks may be substantially the size of the kerf produced by the cutting such that the dice are separated from the other wafer by the cutting step. Alternately, the peaks may have a width greater than the kerf produced by the cutting and remain attached to the other wafer by the remaining peak portions. The dice are then separated from the other wafer at the remaining peak portions by an additional step.

Abstract: A dielectric isolated area is formed by bonding a first and a second wafer. A first wafer having a first and a second major surface is provided. A second wafer having a first and a second major surface is then provided. Trenches are formed in the first surface of the second wafer. Subsequently, a dielectric layer which can be planarized is formed on the surface of the second wafer having trenches formed therein. The first and second wafers are then bonded so that the dielectric layer and the first surface of the first wafer are bonded to each other. A portion of the second surface of the second wafer is then removed down to at least the bottom of each trench.

Abstract: Front end processing for a CMOS substrate resulting in the formation of n-wells, p-wells, channel stops and field oxide regions. Both the n-type and p-type dopant are implanted through silicon nitride members with one type dopant being first blocked by a first layer of photoresist and the second dopant by a second layer of photoresist. The field oxide regions are grown after the first dopant is implanted. Relatively low level ion implantation is used and additional threshold adjusting implants are not needed.

Abstract: A method for processing heavy crude oils comprising a) atmospheric distillation of a heavy crude oil having a high content of metals, asphaltenes and sulfur; b) solvent extraction of the atmospheric distillation residue to obtain an extract with characteristics equivalent to those which an atmospheric residue derived from light crude oil and a raffinate fraction, solid at ambient conditions, in which are concentrated the asphaltenes, metals and sulfur present in the original crude oil; c) vacuum distillation of the deasphalted extract, obtaining a light fraction or gas oils with characteristics adequate to be subjected to a secondary conversion process, plus a bottoms fraction or vacuum residue; d) treatment of the vacuum gas oils in a conversion stage and e) subjecting the bottoms of raffinate from the extraction stage to a metallurgical process, in admixture with cokeable coal and coke fines to production of metallurgical coke.

Abstract: A low-stress process for creating field isolation regions on a silicon substrate that are fully recessed with respect to active areas. The field isolation regions, which have no bird's beak transition regions at their edges, are created by oxidizing an epitaxially-grown layer of silicon, the edges of which are isolated from active area silicon by a an oxide-backed silicon nitride spacer. Each nitride spacer is contiguous with a horizontal silicon nitride layer segment that protects an active area from oxidation during thermal field oxidation. A modification of the process, which requires the deposition of an additional silicon dioxide layer and a wet etch to remove spacers created from that additional layer, further reduces stress during thermal oxidation of the epitaxially-grown silicon layer by providing a void around the periphery of the epitaxial layer for expansion during the thermal oxidation thereof.

Abstract: An isolation structure and method of fabrication thereof for use in isolation of p-n junctions and for use in multiplexed, multi-color LED arrays. The isolation structure is fabricated on a structure which has a p-n junction formed on a semi-insulating substrate by (1) diffusing dopants into predetermined regions thereof from the top of the structure to the semi-insulating substrate, the dopants being of the same dopant type as that contained in the top layer of the p-n junction and (2) ion-implanting predetermined regions of the top layer of the p-n junction to render them non-conductive.

Abstract: An electronic device of the type including a thin film body having a superposed metallic electrode has short circuit defects therein passivated by a conversion process in which the electrical resistivity of the metallic electrode material is increased proximate the defect regions. Conversion is accomplished by exposing the metallic electrode material to a conversion reagent and activating the reagent proximate the defect regions. The process may be utilized for a variety of differently configured devices, and may be readily adapted for use in a roll-to-roll device fabrication process.

Abstract: The present invention is directed to a process for producing a semiconductor device that has a multilayer interconnection composed of a plurality of conductive layers electrically separated from each other by interlayer insulating layers inserted therebetween in an area other than the sites at which the conductive layers are electrically interconnected via a through hole. At least one of the conductive layers has a layer formed thereon for preventing stress- and/or electro-migration thereof.

Abstract: The present invention relates to a process and an apparatus for steam cracking a mixture of hydrocarbons comprising passing steam and the mixture of hydrocarbons through at least one heated cracking tube. The process is characterised in that it is controlled by analyzing the mixture of hydrocarbons fed to the cracking tube with an infrared spectrophotometer to determine the absorbances at a number n of wavelengths in the range 0.8 to 2.6 microns and by using the results of this absorbance to determine one or more values V of steam cracking process conditions which will achieve a desired value P of the space time yield of one or more products of the steam cracking reaction.

Abstract: The tunnelling area of a EEPROM memory device of the FLOTOX type is efficiently reduced in respect to the minimum areas obtained by means of current fabrication technologies, by forming the injection zone for the transfer of the electric charges by tunnel effect to and from the floating gate through an original self-aligned process, which allows limiting the dimensions of such a tunnelling area independently from the resolution limits of the available photolithographic technology.