Patents Examined by Galina Yushina
  • Patent number: 10256257
    Abstract: A line array structure is provided, including long wirings, short wirings, first dummy wirings and connection lines. The substrate has an elongated region, a protruding region and a drive connection region. The elongated region has first sides and second sides that respectively extend along a long-side and short-side directions. The protruding region protrudes out from the first side and is connected to the elongated region. The drive connection region is connected to the second side of the elongated region. The long wirings are disposed in the elongated region and extend to the drive connection region. The short wirings are disposed in the protruding region and are parallel with the long wirings. The first dummy wirings are disposed in the elongated region and extend to the drive connection region. Each of the short wirings is electrically connected to a corresponding first dummy wiring through one first connection lines.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 9, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Ian French, Chi-Ming Wu, Kuang-Heng Liang, Shu-Fen Tsai, Jia-Hung Chen
  • Patent number: 10256183
    Abstract: The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP comprises portions of a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: April 9, 2019
    Assignee: IMEC
    Inventors: Mikael Detalle, Eric Beyne
  • Patent number: 10236355
    Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10229923
    Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 12, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter, David Daycock
  • Patent number: 10211227
    Abstract: A display substrate includes: a base substrate; a switching device disposed on the base substrate, the switching device including a gate electrode, a source electrode, and a drain electrode overlapping at least a part of the gate electrode; a wavelength converting layer disposed on the switching device, the wavelength converting layer including a quantum dot; a bridge electrode disposed on the wavelength converting layer, the bridge electrode electrically connected to the drain electrode through a first contact hole formed through the wavelength converting layer; a planarizing layer disposed on the wavelength converting layer; and a pixel electrode disposed on the planarizing layer, the pixel electrode electrically connected to the bridge electrode through a second contact hole formed through the planarizing layer.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: February 19, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Taewoo Kim, Eunjung Kim, Moonjung An, Gugrae Jo, Hyungbin Cho
  • Patent number: 10205035
    Abstract: The present invention relates to an electronic proximity sensor having a decorative surface, characterized in that the decorative surface comprises a semiconductor layer, the thickness of which is between 10 nm and 100 nm. This coating imparts a desired metallic appearance to the proximity sensor, without the property thereof as a proximity sensor being lost.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: February 12, 2019
    Assignee: OERLIKON SURFACE SOLUTIONS AG, PFÄFFIKON
    Inventors: Antal Keckes, Peter Schuler, Thomas Hermann
  • Patent number: 10199441
    Abstract: A display panel includes a first substrate, a plurality of first signal lines, a plurality of second signal lines, and a plurality of pixel electrodes. The first substrate has at least one bendable area and two non-bendable areas. The at least one bendable area is located between the two non-bendable areas. One of the first signal lines and one of the second signal lines are electrically connected to at least one subpixel. Each of the a subpixels includes a control unit, and the control units are provided only in the non-bendable areas and are not provided in the bendable area. The pixel electrodes are provided in the bendable area and the non-bendable areas. Each of the controls units is electrically connected to one of the pixel electrodes.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 5, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chan-Jui Liu, Pei-Yun Wang
  • Patent number: 10193034
    Abstract: A semiconductor device includes a semiconductor chip including an active region provided to generate radiation; a radiation exit face extending parallel to a main plane of extension of the active region; a molding directly adjoins at least one side face of the semiconductor device at least one back of the semiconductor chip remote from the radiation exit face; a mounting surface provided to mount the semiconductor device; and a spacer projecting beyond the radiation exit face in a vertical direction extending perpendicular to the radiation exit face.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: January 29, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Matthias Sperl, Frank Singer
  • Patent number: 10186648
    Abstract: A display device includes: a display substrate including: a pixel area provided in plurality separated from each other, and a plurality of through holes separated from each other; a light-emitting diode provided in plurality arranged on the display substrate in the pixel areas thereof; and a wiring line provided in plurality on the display substrate, the wiring line including a first wiring line and a second wiring line which are each electrically connected to the light-emitting diode.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Mugyeom Kim
  • Patent number: 10177164
    Abstract: A stack structure including a plurality of gate electrodes is vertically stacked on a substrate and extends in a first direction. A channel structure includes vertical channels penetrating the stack structure and a horizontal channel connecting the vertical channels. The horizontal channel are provided under the stack structure. First lower wiring patterns are disposed between the substrate and the stack structure and electrically connected to the channel structure. Each first lower wiring pattern includes a first portion and a second portion having different widths from each other in the first direction.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: January 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sunghan Cho, Shinhwan Kang
  • Patent number: 10177139
    Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: January 8, 2019
    Assignee: Butterfly Network, Inc.
    Inventors: Jonathan M. Rothberg, Keith G. Fife, Nevada J. Sanchez, Susan A. Alie
  • Patent number: 10177285
    Abstract: A method of producing a housing cover includes providing a cover blank having a mounting surface formed on an underside; connecting the underside of the cover blank to a silicon slice; creating at least one opening in the silicon slice to expose at least part of the mounting surface; arranging a base metallization on the exposed part of the mounting surface; and removing the silicon slice.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: January 8, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Tilman Ruegheimer, Juergen Dachs
  • Patent number: 10170572
    Abstract: A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed with a two-step etching process as described in detail in the specification. The devices that embody this invention can be fabricated with higher packaging density and better and more tightly distributed device parameters such as the VF, RDSS, and BV.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: January 1, 2019
    Assignee: Diodes Incorporated
    Inventors: Yun-Pu Ku, Chiao-Shun Chuang, Cheng-Chin Huang
  • Patent number: 10163981
    Abstract: The present disclosure relates to an integrated circuit having an interconnect wire contacting an upper electrode of the RRAM (resistive random access memory) device, and a method of formation. In some embodiments, the integrated circuit comprises an RRAM device having a dielectric data storage layer disposed between a lower electrode and an upper electrode. An interconnect wire contacts an upper surface of the upper electrode, and an interconnect via is arranged onto the interconnect wire. The interconnect via is set back from one or more outermost sidewalls of the interconnect wire. The interconnect wire has a relatively large size that provides for a good electrical connection between the interconnect wire and the upper electrode, thereby increasing a process window of the RRAM device.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsia-Wei Chen, Chih-Yang Chang, Chin-Chieh Yang, Jen-Sheng Yang, Kuo-Chi Tu, Wen-Ting Chu, Yu-Wen Liao
  • Patent number: 10164020
    Abstract: A semiconductor device may include an n? type layer disposed at a first surface of an n+ type silicon carbide substrate; a p? type region, a p type region, an n+ type region, and a p+ type region disposed at an upper portion in the n? type layer; a gate electrode and a source electrode disposed on the n? type layer and insulated from each other; and a drain electrode disposed at a second surface of the n+ type silicon carbide substrate, wherein the source electrode is in contact with the p? type region, the n+ type region, and the p+ type region, and the source electrode may include an ohmic junction region disposed at a contact portion of the source electrode and the n+ type region and the contact portion of the source region and the p+ type region and a Schottky junction region disposed at the contact portion of the source electrode and the p? type region.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: December 25, 2018
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Dae Hwan Chun, NackYong Joo
  • Patent number: 10157911
    Abstract: In a semiconductor device having an SJ structure, the reverse breakdown voltage decrease is suppressed while a main body region and a current detecting region are separated. Provided is a semiconductor device that has a semiconductor substrate, a main body region including one or more operation cells formed inside the semiconductor substrate, a current detecting region including one or more current detecting cells formed inside the semiconductor substrate, and an intermediate region that is provided between the main body region and the current detecting region and inside the semiconductor substrate and that includes an edge termination structure unit. A first conductivity-type column and a second conductivity-type column are alternately arranged at equal intervals in the main body region, the current detecting region, and the intermediate region.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: December 18, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Takeyoshi Nishimura
  • Patent number: 10158047
    Abstract: Disclosed is a semiconductor light emitting device including: a plurality of semiconductor layers; a first non-conductive reflective film formed on the plurality of semiconductor layer to reflect light from the active layer, wherein the first non-conductive reflective film includes multiple layers and has a first incident angle as the Brewster angle; a second non-conductive reflective film formed on the first non-conductive reflective film to reflect light transmitted through the first non-conductive reflective film, wherein the second non-conductive reflective film includes multiple layers, with part of which being made of a different material from the first non-conductive reflective film, and has a second incident angle as the Brewster angle, different from the first incident angle; and an electrode electrically connected to one of the plurality of semiconductor layers.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: December 18, 2018
    Assignee: SEMICON LIGHT CO., LTD.
    Inventors: Soo Kun Jeon, Jun Chun Park, Il Gyun Choi, Sung Gi Lee, Dae Soo Soul, Tea Jin Kim, Yeon Ho Jeong, Geun Mo Jin, Sung Chan Lee
  • Patent number: 10157937
    Abstract: A TFT array substrate includes a display zone having data lines, scan lines, and sub-pixels arranged in an array. For the sub-pixels of the same row, each of the sub-pixels of the even columns is connected with the scan line above the row of the sub-pixels and each of the sub-pixels of the odd columns is connected with the scan line below the row of the sub-pixels. The non-display zone includes fan-out lines respectively corresponding to and connected with the scan lines. Each of the fan-out lines includes a horizontal line segment and a slanted line segment. The slanted line segments of the two fan-out lines respectively corresponding to and connected with two adjacent, upper and lower scan lines are arranged to intersect each other in a mutually isolated manner so as to change the sequence of driving the two adjacent, upper and lower scan lines.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: December 18, 2018
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventor: Caiqin Chen
  • Patent number: 10141442
    Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.
    Type: Grant
    Filed: January 19, 2016
    Date of Patent: November 27, 2018
    Assignee: INTEL CORPORATION
    Inventor: Mark T. Bohr
  • Patent number: 10134737
    Abstract: An interconnect structure includes a lower interconnect layer, an intermediate interconnect layer, and an upper interconnect layer. First and second conductive lines in the lower interconnect layer extend generally in a first direction over a memory array region, and additional lower conductive lines in the lower interconnect layer extend generally in the first direction over a peripheral region. A first plurality of conductive line segments in the intermediate interconnect layer extend generally in the first direction over the memory array region, and additional intermediate conductive line segments in the intermediate interconnect layer extend generally in a second, perpendicular direction over the peripheral region. A second plurality of conductive line segments in the upper interconnect layer extend generally in the first direction over the memory array region, and additional upper conductive line segments in the upper interconnect layer extend generally in the first direction over the peripheral region.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Yen-Huei Chen