Abstract: A semiconductor chip may include a semiconductor substrate and a crack detection circuit. The semiconductor substrate may include a circuit structure. The crack detection circuit may include main lines and a chamfer lines. The main lines may be formed in the semiconductor substrate to surround the circuit structure. The chamfer lines may be formed in corners of the semiconductor substrate. The chamfer lines may be connected between the main lines. A first angle may be formed between each of the chamfer lines and any one of the two main lines perpendicular to each other. A second angle wider than the first angle may be formed between each of the chamfer lines and the other main line.

Abstract: A method includes coining solder balls of a bottom package, wherein top surfaces of the solder balls are flattened after the step of coining. The solder balls are molded in a molding material. The top surfaces of the solder balls are through trenches in the molding material.

Abstract: A semiconductor structure comprising a substrate, a pre-metal-interconnect dielectric (PMID) layer and a composite layer is disclosed. The PMID layer is above the substrate. The composite layer is between the substrate and the PMID layer. The composite layer comprises a first sublayer and a second sublayer. The first sublayer and the second sublayer are stacked. The bandgap of the second sublayer is larger than the bandgap of the first sublayer. The etch rate of an etchant with respect to the first sublayer is lower than the etch rate of the etchant with respect to the substrate and the PMID layer. Other semiconductor structures are also disclosed.

Abstract: A flexible display device including a substrate having an active region in which an input image is implemented and a bezel region outside the active region; a signal line (or an electrode) extending from the bezel region and transmitting a signal (or a voltage) to the active region; and a first bypass line provided above or below the signal line with one or more insulating layers interposed therebetween in the bezel region, wherein the first bypass line is connected to the signal line via a first bypass contact hole penetrating through the one or more insulating layers and receives the same signal as that of the signal line, and wherein the first bypass contact hole is provided as at least two bypass contact holes.

Abstract: A method of manufacturing a device having a microelectronic component housed in a hermetically sealed vacuum housing, including forming a getter in said housing, pumping out and heating the device to degas elements housed in said housing, after said pumping, hermetically sealing the housing in fluxless fashion. Further, each material forming the device likely to degas into the inner space is a mineral material, the getter is capable of substantially trapping hydrogen only and is inert to oxygen and/or to nitrogen and the heating and the sealing are performed at a temperature lower than 300° C.

Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.

Abstract: An LED element is provided with: a first semiconductor layer formed of an n-type nitride semiconductor; a second semiconductor layer formed on top of the first semiconductor layer and formed of quaternary mixed crystals of Alx1Gay1Inz1N (0<x1<1, 0<y1<1, 0<z1<1 and x1+y1+z1=1); a heterostructure formed on top of the second semiconductor layer and constituted of a laminate structure of a third semiconductor layer formed of Inx2Ga1-x2N (0<x2<1) having a film thickness of greater than or equal to 10 nm, and a fourth semiconductor layer formed of Alx3Gay3Inz3N (0<x3<1, 0<y3<1, 0?z3<1 and x3+y3+z3=1); and a fifth semiconductor layer formed on top of the heterostructure and formed of a p-type nitride semiconductor.

Abstract: A pixel circuit and a pixel structure having high aperture ratio are provided. A first gate electrode, a layer including a first source electrode and a first drain electrode, and an etching stopper layer, a first semiconductor layer, and a gate isolation layer sandwiched between the first gate electrode and the layer of the first source electrode and the first drain electrode construct a first thin film transistor. A second gate electrode, a layer including a second source electrode and a second drain electrode, and an etching stopper layer, a second semiconductor layer, and the gate isolation layer sandwiched between the second gate electrode and the layer of the second source electrode and the second drain electrode construct a second thin film transistor. An isolation layer with a flat top surface is sandwiched between a transparent electrode and a pixel electrode to form a transparent capacitor.

Abstract: A light-emitting device includes a semiconductor layered structure; an upper electrode disposed on a portion of an upper surface of the semiconductor layered structure; a lower electrode disposed on a lower surface of the semiconductor layered structure in a region spaced from a region directly under the upper electrode, the lower electrode being reflective; and a protective film disposed continuously on a surface of the upper electrode and the upper surface of the semiconductor layered structure. A thickness of a first portion of the protective film, which is disposed at least in a region directly above the lower electrode, is smaller than a thickness of a second portion of the protective film, which is disposed continuously on the surface of the upper electrode and the upper surface of the semiconductor layered structure adjacent to the portion on which the upper electrode is disposed.

Abstract: Semiconductor devices with enclosed cavities and methods for fabricating semiconductor devices with enclosed cavities are provided. In an embodiment, a method for fabricating a semiconductor device with a cavity includes forming a sacrificial structure in and/or over a substrate. The method includes depositing a permeable layer over the sacrificial structure and the substrate. Further, the method includes etching the sacrificial structure through the permeable layer to form the cavity bounded by the substrate and the permeable layer.

Abstract: A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced ?VT (variation in VT) compared to conventional bulk CMOS and can allow the threshold voltage VT of FETs having dopants in the channel region to be set much more precisely. A novel dopant profile indicative of a distinctive notch enables tuning of the VT setting within a precise range. This VT set range may be extended by appropriate selection of metals of a gate electrode material so that a very wide range of VT settings is accommodated on the die. The DDC design also can have a strong body effect compared to conventional bulk CMOS transistors, which can allow for significant dynamic control of power consumption in DDC transistors. The result is the ability to independently control VT (with a low ?VT) and VDD (the operating voltage supplied to the transistor), so that the body bias can be tuned separately from VT for a given device.

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

Abstract: A liquid crystal display device includes a pixel electrode that includes a first central portion and a first stem portion and sequentially disposed on one side of a reference line extending in a first direction, and a second central portion and a second stem portion sequentially disposed on the other side, where the first stem portion extends at a first oblique angle in which a center line of a line width has a positive sign with respect to the first direction, the first central portion extends from one end of the first stem portion and has a shape in which a center line of the line width is inclined at a second oblique angle having a positive sign with respect to the first direction, and a line width of the first central portion is smaller than the line width of the first stem portion.

Abstract: A heterojunction bipolar transistor, comprising an elongated base mesa, an “H” shaped emitter, two base electrodes, an elongated collector, and two elongated collector electrodes. The “H” shaped emitter is formed on the base mesa and has two parallel bars connected by a cross-bar. Two elongated emitter electrodes are formed respectively on the two parallel bars of the “H” shaped emitter. The “H” shaped emitter has two recesses respectively on two opposite sides of the cross-bar between the two parallel bars. The two base electrodes are formed on the base mesa respectively at the two recesses of the “H” shaped emitter, each of which has a base via hole near a center of the base mesa. The elongated collector is formed below the base mesa. The two elongated collector electrodes are formed on the collector respectively at two opposite sides of the base mesa.

Abstract: The present disclosure provides an array substrate, a flexible display device, and a method for manufacturing an array substrate. The array substrate includes a flexible substrate arranged at a display region and a peripheral region, and an array layer formed on the flexible substrate. The flexible substrate arranged at the display region has a first thickness, and at least a portion of the flexible substrate arranged at the peripheral region has a second thickness greater than the first thickness. According to the array substrate of the present disclosure, the flexible substrate arranged at the peripheral region is provided with a thickened portion so as to meet the strength requirement of an unfoldable region. Meanwhile, the thickened portion can be formed in a single process through a base plate having a corresponding concave structure, and as a result, it is able to reduce the process complexity.

Abstract: A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.

Abstract: A semiconductor device includes a pair of erase gate lines, a pair of control gate lines and a pair of word lines. The pair of control gate lines are disposed on the erase gate lines. Each one of the control gate lines includes a plurality of segments between which portions of one of the pair of erase gate lines are seen in a plan view. In a plan view of the semiconductor device, the pair of word lines are disposed between the control gate lines and extending along edges of the control gate lines.

Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.

Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract: A semiconductor device and a method for fabricating the semiconductor device have been provided. The method for fabricating a semiconductor device includes the steps of: forming a channel layer on a substrate; forming a gate dielectric layer on the channel layer; forming a source layer and a drain layer adjacent two sides of the gate dielectric layer; forming a bottom gate on the gate dielectric layer; forming a phase change layer on the bottom gate; and forming a top gate on the phase change layer.