Patents Examined by Gareth D. Shaw
  • Patent number: 5301314
    Abstract: A computer-aided customer support system is described for rapidly retrieving stored documents useful in answering customer inquiries. A hierarchical index tree is used in which an indexing document is referenced at each level as the search proceeds down through the various tiers. Once the targeted document is retrieved and reviewed, the user is interrogated by the system as to the usefulness of the document in solving the customer's inquiry. Based on the response to this interrogation, the usefulness priority and location of this document within the tree structure are reevaluated.
    Type: Grant
    Filed: August 5, 1991
    Date of Patent: April 5, 1994
    Assignee: Answer Computer, Inc.
    Inventors: Rick L. Gifford, Elizabeth Anderson, Louise Kirkbride, John T. Evans, Jr.
  • Patent number: 5299317
    Abstract: A method and apparatus are described for simulating on one multi-stage interconnection network (MIN) the operation of a second MIN. By means of two algorithms we generate first and second vectors, I.sub.1, O.sub.1, which characterize the first MIN and by means of the same two algorithms we generate third and fourth vectors, I.sub.2 O.sub.2, which characterize the second MIN. We then generate fifth and sixth vectors, U, V, where U=O.sub.2 * O.sub.1.sup.-1 and V=I.sub.1.sup.-1 * I.sub.2 where O.sub.1.sup.-1 and I.sub.1.sup.-1 are the inverses, respectively, of O.sub.1 and I.sub.1 and * is a two-operand permutation operation which permutes elements of a first operand (e.g., O.sub.2) in accordance with an order specified by a second operand (e.g., O.sub.1.sup.-1). The fifth vector is then used to reorder the inputs to the first MIN; and the sixth vector is used to reorder the outputs from said first MIN.
    Type: Grant
    Filed: October 2, 1992
    Date of Patent: March 29, 1994
    Assignee: Syracuse University
    Inventors: Chien-Yi R. Chen, Jyan-Ann C. Hsia
  • Patent number: 5297283
    Abstract: An object based operating system for a multitasking computer system provides objects which represent the architecture or interrelationships of the system's resources. Access to certain objects is required in order to use corresponding resources in the system. All objects have a consistent data structure, and a consistent method of defining the operations which apply to each type of object. As a result, it is relatively easy to add new types of system objects to the operating system. The object based operating system supports multiple levels of visibility, allowing objects to be operated on only by processes with the object's range of visibility. This allows objects to be made private to a process, shared by all processes within a job, or visible to all processes within the system. An object or an entire set of objects can be moved to a higher visibility level when objects need to be shared.
    Type: Grant
    Filed: October 16, 1992
    Date of Patent: March 22, 1994
    Assignee: Digital Equipment Corporation
    Inventors: James W. Kelly, Jr., Frank L. Perazzoli, Jr., David N. Cutler
  • Patent number: 5297257
    Abstract: A method for a distributed processing system which includes the steps of developing a control program for controlling outputs at a plurality of I/O nodes, distributing executable portions of the program to the I/O nodes through a network, broadcasting input status data from the I/O nodes on the network and controlling the outputs at the I/O nodes in response to the input status data broadcast on the network and the executable portions of the program residing at the I/O nodes.
    Type: Grant
    Filed: April 15, 1991
    Date of Patent: March 22, 1994
    Assignee: Allen-Bradley Company, Inc.
    Inventors: Odo J. Struger, Ernst Dummermuth
  • Patent number: 5297281
    Abstract: A digital computer includes a main and an auxiliary pipeline processor which are configured to concurrently execute contiguous groups of instructions taken from a single instruction sequence. The instructions in a sequence may be divided into groups by using either taken-branch instructions or certain instructions which may change the contents of the general purpose registers as group delimiters. Both methods of grouping the instructions use a branch history table to predict the sequence in which the instructions will be executed.
    Type: Grant
    Filed: February 13, 1992
    Date of Patent: March 22, 1994
    Assignee: International Business Machines Corporation
    Inventors: Philip G. Emma, Joshua W. Knight, James H. Pomerene, Rudolph N. Rechtschaffen, Frank J. Sparacio
  • Patent number: 5297285
    Abstract: A method for dynamically modifying addressing information within a modular software system controlling a telecommunications switching system. Conventional telecommunications exchanges divide each exchange into discrete function blocks with a limited number of functions being performed by each block, thus requiring frequent interaction between blocks through the exchange of software signals. Such exchanges are more complicated in stored program control systems in which individual blocks are removed from memory and reloaded in different memory locations and in which revised blocks contain modified symbol addresses. The present invention utilizes a global signal distribution table loaded with global signal numbers for types of software signals, as well as local signal numbers of corresponding tasks given function blocks. This method overcomes disadvantages typically associated with linking and loading of software modules by delaying linking and performing it dynamically as each block is executed.
    Type: Grant
    Filed: July 23, 1991
    Date of Patent: March 22, 1994
    Assignee: Telefonaktiebolaget L M Ericsson
    Inventors: Anders Abrahamsson, Lars Holmquist
  • Patent number: 5295262
    Abstract: A system and method for maintaining linked data structures stored in a computer system capable of processing the stored data as addressable object nodes, such that any data object node may be modified prior to the completion of outstanding read only accesses to that node. The system and method maintain an access vector for each node. The access vectors include an access counter which counts the number of read only accesses from a present node to the next node, and a link pointing to a next node. The number of read only accesses in effect for a node is the sum of access counts of all access vectors pointing to that node, minus the ADJ and minus the sum of access counts of all access vectors with access to that node. A node in the list can be replaced or deleted by first changing the pointers of all nodes that point to the node to point to a new one. Then, modifying the access count of the node by subtracting the maximum value of the access counts pointing to the node from the count in the node.
    Type: Grant
    Filed: May 16, 1991
    Date of Patent: March 15, 1994
    Assignee: International Business Machines Corporation
    Inventor: Joseph W. Seigh, II
  • Patent number: 5293618
    Abstract: In an information processing system including a file shared by computer systems each having a central processing system and a main memory, a method for controlling access to the shared file includes a step of storing blocks read from the file into the main memory when the blocks of the file are updated, and a step of comparing at least a portion of the blocks held in a cache memory with at least a portion of the blocks stored in the main memory. When the comparison of at least the portion of the blocks held in the cache memory with at least the portion of the blocks stored in the main memory indicates mismatching, the block is read from the file into the main memory, and when the comparison indicates matching, the block of the main memory is updated. The data to be updated may be in a resident area, an input/output buffer or a same area.
    Type: Grant
    Filed: November 15, 1990
    Date of Patent: March 8, 1994
    Assignees: Hitachi, Ltd., Hitachi Software Engineering Co, Ltd
    Inventors: Michio Tandai, Masaaki Hama, Fujio Fujita
  • Patent number: 5293620
    Abstract: A task dispatch system for use in connection with a plurality of digital data processors for processing tasks. The task dispatch system maintains a task identification queue including a plurality of task identification entries defining a series of tasks to be processed during an iteration. A task dispatcher dispatches tasks to the processors in the order defined by the task identification queue. At the end of an iteration, the task dispatcher reorganizes the entries in the task identification queue so as to dispatch one or more tasks, which were completed last during an iteration, at the beginning of a subsequent iteration.
    Type: Grant
    Filed: August 10, 1992
    Date of Patent: March 8, 1994
    Assignee: Digital Equipment Corporation
    Inventors: William Barabash, William S. Yerazunis
  • Patent number: 5293500
    Abstract: A parallel processor is provided with a plurality of independently operable command units and a plurality of function units each connected to the command unit. A data unit, a register file, and a carry bit are shared such that the command and function units operate in parallel without any conflict. A priority scoreboard is provided to control the register file so that the command units operate independently according to the parallelism of a program, and detect and avoid a contention for a register according to the order of priority, making simultaneous execution of a plurality of commands possible, resulting in the increased process speed.
    Type: Grant
    Filed: May 27, 1993
    Date of Patent: March 8, 1994
    Assignee: Mitsubishi Denki K.K.
    Inventors: Hitoshi Ishida, Shigeyuki Kazama, Minoru Shiga
  • Patent number: 5293492
    Abstract: In a data processing system having a data path (30) between a memory device (11) and input-output devices (12), and a holding device (18) for holding first through N-th firmware data, where N represents an integer greater than one, an input-output processor (13) comprises first through N-th control memory layers of control memories (31, 32, 33) and a data controller (34) connected to the holding device. Responsive to a firmware load instruction (23), the data controller reads the first through the N-th firmware data from the holding device as first through N-th read-out data. The holding device makes the memory device memorize the first through the N-th read-out data as first through N-th memorized data. Connected to the control memories, the data controller makes the control memories of the first through the N-th control memory layers memorize the first through the N-th memorized data through the data path.
    Type: Grant
    Filed: August 31, 1989
    Date of Patent: March 8, 1994
    Assignee: NEC Corporation
    Inventors: Hajime Oyadomari, Toru Fukuta
  • Patent number: 5291595
    Abstract: A process for executing batch files and application programs by storing the batch files and information about the application programs together as modules inside a parent file, such that each module may be extracted from the parent and executed independently of any other module according to its type. Access to the module is through a menu which provides for each module the name of the module and optionally a phrase descriptive of the module. Batch modules may be relocated to RAM disks for faster execution. When running a batch module, the process of this invention cedes all its memory to the batch module. Program information modules are checked to determine if they provide a program specification or a path specification: if program specification, the program is executed; if path specification, executable files from the specified directory are retrieved and displayed for execution as desired.
    Type: Grant
    Filed: July 7, 1992
    Date of Patent: March 1, 1994
    Inventor: Augusto B. Martins
  • Patent number: 5291598
    Abstract: A system to control the use of an informational product is disclosed. The informational product is stored on a storage medium and executed by a first processor. The informational product is operatable in a plurality of modes. The system comprises three manufacture modules. The first manufacture module, executed by the first processor, generates a registration code for a user of the informational product, the registration code being a function of the identity of the first processor, the identity of the user and the identity of the informational product. The second manufacture module, executed by the first processor, accepts as input an authorization code, verifies the authorization code and, if the verification is successful, changes the operational mode of the informational product. The second manufacture module also stores a user record in the informational product. The third manufacture module examines the user record each time the informational product is activated.
    Type: Grant
    Filed: April 7, 1992
    Date of Patent: March 1, 1994
    Inventor: Gregory Grundy
  • Patent number: 5291596
    Abstract: A data management system comprising, a management device, wherein the management device comprises, a plurality of data, a table formation device for forming a management table indicating respective conditions of a right of use for each one of the plurality of data, a use authorization determination device for determining whether a request for the right of use for one of the plurality of data is authorized by reference to the management table, and a use allocation device for granting the right of use for one of the plurality of data on the basis of a determination by the use authorization determination device.
    Type: Grant
    Filed: February 16, 1993
    Date of Patent: March 1, 1994
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Makoto Mita
  • Patent number: 5291601
    Abstract: A method and apparatus for running a computer program containing references to a library utilizes a load time linker to insert addresses of referenced library items directly into the program code at run-time. The linking loader causes a delay that is not objectionable to the user. The method includes the steps of maintaining in computer memory a shared library including library items and a library symbol table. A relocatable file representing the computer program is loaded into the computer memory when the computer program is to be run. Addresses of library items that are referenced in the program code are found in the library symbol table, and the addresses of the library items are inserted directly into the program code of the relocatable file in computer memory. After the relocatable file is loaded from disk to memory, all operations are performed in computer memory, resulting in high speed operation.
    Type: Grant
    Filed: March 27, 1992
    Date of Patent: March 1, 1994
    Assignee: Hewlett-Packard Company
    Inventor: Samuel C. Sands
  • Patent number: 5291599
    Abstract: A computer partitioner provides services to several partitions coexisting in a computer at one time. To operate efficiently, certain applications executing within a partition will intermittently require specific services to be delivered to them in a timely fashion. This disclosure provides a mechanism for a computer partitioner to provide special time dependent services to partitions on a dynamic demand basis.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: March 1, 1994
    Assignee: International Business Machines Corporation
    Inventors: Edward I. Cohen, Michael R. Sheets
  • Patent number: 5289585
    Abstract: A microprocessor system has a bus system for coupling several processing units, each having an appertaining private cache memory and a common main memory. When an address operation of a transaction is executed, a transaction identification number is generated and transmitted on the system bus to all other subscribers together with the fed address of the initiating subscriber. In each subscriber, memory means are provided for storing the transmitted address and the co-delivered transaction identification number. Simultaneously with the assignment of the system bus for further transmissions, the address stored in the memory means are monitored in test means of the subscribers, and after monitoring, a synchronization signal and possibly accompanying signals are set by all subscribers for the abortion or continuation of a transaction.
    Type: Grant
    Filed: July 22, 1992
    Date of Patent: February 22, 1994
    Assignee: Siemens Nixdorf Informationssysteme AG
    Inventors: Juergen Kock, Peter Mooshammer, Wilfried Rottmann, Erich Taeuber
  • Patent number: 5287514
    Abstract: Methods for allowing a user to customize an interface for a computer program are provided The methods allow a user of the computer program flexibility in organizing commands into a menu structure The methods also allow a user of a computer program to assign a keystroke sequence to a command. The user can then invoke the command by entering the keystroke sequence. A command assigned to a keystroke sequence does not need to be associated with a menu. The methods allow the user of a computer program to predefine parameters for commands. The predefinition allows the user to invoke a command without reentering the parameters. In a preferred embodiments, the methods use a command array that contains an entry for each command. The methods use an array associated with each menu. The arrays contain unique identifiers of the commands that are associated with the menu. These unique identifiers are used to reference entries into the command array.
    Type: Grant
    Filed: January 10, 1992
    Date of Patent: February 15, 1994
    Assignee: Microsoft Corporation
    Inventor: Raymond D. Gram
  • Patent number: 5287502
    Abstract: A method of obtaining a desired function from a computer system by selecting one or more pictorial symbols displayed on a display screen is disclosed. The method comprises the steps of providing a plurality of attributes to at least part of the plurality of pictorial symbols, inferring by using a predetermined rule in accordance with the attributes when one or more of the plurality of pictorial symbols is selected, and obtaining a function of the computer system in accordance with the inferred result.
    Type: Grant
    Filed: September 11, 1991
    Date of Patent: February 15, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Satomi Kaneko
  • Patent number: 5287509
    Abstract: A system for multitasking inner loops, such as DO loops, using multiprocessors, provided with a plurality of shared registers each corresponding to one of a plurality of individual processors comprising the multiprocessor system. The plurality of shared registers store start and end values of segments resulting from dividing ranges of loop variables corresponding to the inner loops. The system for multitasking inner loops comprises an executing unit for iteratively executing the processing of the inner loops until the end value is reached. The system also comprises a decision unit for deciding whether or not there remain any unprocessed loops. Finally, the system comprises a continuing unit, responsive to the decision unit for continuing processing of the unprocessed loop or loops by transferring a part of a range which the loop variables corresponding to the unprocessed loop or loops can have.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: February 15, 1994
    Assignee: NEC Corporation
    Inventor: Shouichirou Yamada