Abstract: A method of proactively event triggering in a computer system is disclosed. The computer system includes an application unit and an interface. The method includes the application unit sending a setting signal to change a voltage level of a pin of a control chip module; the pin generating a triggering event to the interface unit when the voltage level of the pin changes; and the interface accessing a controller according to the triggering event to allow the application unit to communicate with the controller proactively.

Abstract: A method provides processor initialization in different platform environments via a single code set. The method includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The method further includes performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated. The HWP framework includes standard interfaces and enables direct updates to hardware procedures without requiring a new flash code or a firmware patch.

Abstract: A system and computer program product provide processor initialization in different platform environments via a single code set. The system includes: in response to detecting a power-on operation of the processor, a microcontroller retrieving hardware procedures (HWP) framework code from a storage and triggering execution of the HWP framework code on the processor. The execution of the HWP framework code generates a HWP framework that comprises a plurality of application programming interfaces (APIs) which govern how all communication processes involving hardware procedures can be accomplished. The system further includes the microcontroller performing one or more initialization procedures by communicating one or more attribute data via the HWP framework to configure the processor for operation within a specific platform environment in which the processor is to be operated.

Abstract: A power distribution system includes a chassis with a plurality of ports that include a first port configured to communicate with powering devices and a second port configured to communicate with powered devices. A power distribution engine in the chassis is coupled to each of the plurality of ports. The power distribution engine determines that power available to the power distribution engine is insufficient to power a first powered device that is coupled to the first port, requests power from a first powering device that is coupled to the second port, and provides power that is received through the second port from the first powering device to the first powered device through the first port. In an embodiment, the first powered device and the second powered device are switch IHSs, the first port is configured as a trunk port, and the second port is configured as an access port.

Abstract: A timing control circuit includes a first variable-delay circuit, a multiplexer, a second variable-delay circuit, a decision circuit, and a control circuit. The first variable-delay circuit receives first data having a first communication speed and delays the first data by a variable delay. The multiplexer receives a first variable-delay circuit output and converts, based on a first control signal, the first data into second data having a second communication speed different from the first communication speed. The second variable-delay circuit receives third data having the first communication speed, and delays the third data by another variable-delay corresponding to the variable-delay of the first variable-delay circuit. The decision circuit compares a second variable-delay circuit output phase and a first control signal phase.

Abstract: When generating a suspend request for a system running on an apparatus, data is stored to a non-volatile memory as a hibernation image which represents a memory state of a volatile memory, register values of a peripheral, and register values of a processor. When generating a boot request of the system, it is determined whether a valid hibernation image is available in the non-volatile memory. When the valid hibernation image is available, a boot core of the processor initializes a part of slave cores of the processor, and the boot core and/or the initialized slave core initialize the peripheral to perform a kernel initialization of the system. After the kernel initialization is completed, the memory state, and the register values of the peripheral and processor are restored based on the valid hibernation image.

Abstract: Managing power rails, including: a plurality of power rails, each power rail coupled to at least one power supply and configured to support a plurality of similarly-configured loads; and a power rail controller configured to merge and split the plurality of power rails based on total power consumption of the plurality of similarly-configured loads. The power rail management also determines the optimal power rail mode (merge/split) based on current load of each rail and adjusts the dynamic clock and voltage scaling policy, workload allocation on each core, and performance limit/throttling management according to the power rail mode.

Abstract: Disclosed is a board including a semiconductor device including a first terminal to receive a signal that sets a functionality of the device, a second terminal to supply a first value and a third terminal to supply a second value, a first connection member connected to the first to third terminals of the semiconductor device, and a second connection member adapted to be connected to the first connection member provided on a counterpart board, with at least two terminals of the second connection member connected together via a first connection circuit, wherein the first connection member of the board is connected to the second connection member of another counterpart board.

Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the cores to control power consumption of the processor. In turn, the PCU includes a control logic to cause the processor to re-enter a first package low power state responsive to expiration of an inter-arrival timer, where this expiration indicates that a time duration subsequent to a transaction received in the processor has occurred. Other embodiments are described and claimed.

Abstract: A computing system includes at least a first division and a second division. The first division has a first clock rate and the second division has a second clock rate. The computing system includes a first processor configured to execute a task on the first division and a second processor configured to execute the task of the second division. The task executed on the first division operates according to the first clock rate, and the task executed on the second division operates according to the second clock rate. A method of executing a task in order to reduce common mode failures in a computing system includes varying a program speed of each of the plurality of divisions such that the task, when executed on a corresponding one of the plurality of divisions, operates at a clock rate according to the corresponding one of the plurality of divisions.

Abstract: A multicore computer architecture provides for clock dividers on each core, the clock dividers capable of providing rapid changes in the clock frequency of the core. The clock dividers are used to reduce the clock frequency of individual cores spinning while waiting for a synchronization instruction resolution such as a lock variable. Core power demands may be decreased before and after change in dock speed to reduce power bus disruption.

Abstract: A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

Abstract: An energy efficient sleep signature in power over Ethernet. In one embodiment, a signature of a powered device is first detected. It is then determined whether the detected signature is indicative of an unknown powered device. In one example, a detected signature of an approximately 25 k? impedance is indicative of an unknown powered device. Where the detected signature is indicative of an unknown powered device a normal PoE startup powering process can be used that includes a conventional detection, classification and powering process. Where the detected signature is indicative of a powered device that was previously known to the PSE, then powering of the PD can proceed with a fast-restart powering method that retains previous powering parameters.

Abstract: A method for creating an offline script format driver file from an INF file includes replacing variables with associated value data. Version data and a unique identifier are captured and stored. Disk identification data is retrieved and combined with data that references the disk identification data in order to create and store a list of disk names and files within those disk names. A list is created of all possible models sections from value data included in a manufacturer value name to determine which models sections support which operating systems. Information that describes which models section is compatible with which operation system is created and stored. For DDInstall sections that include device driver installation details, sections directives that include registry actions or file actions are processed. The method provides an offline script format driver file that is operable to provide for offline driver installation in an information handling system (IHS).

Abstract: A method and computer program product for implementing the method, where the method comprises obtaining boot dependencies among a plurality of systems, wherein a boot dependency identifies a dependent system, a service system that provides a service to the dependent system, a provide state of the service system, and a need state of the dependent system that requires the service system to have reached the provide state. The method further comprises obtaining historical measurements of the time periods between states for each of the systems. Then, during a process of booting the plurality of systems, the method initiates boot of each dependent system at a time that is determined, based on the historical measurements, to allow the dependent system to reach the need state no earlier than the time at which the service system is determined, based on the historical measurements, to reach the provide state.

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the off times each correspond to a maximum off time for a platform including the processor. Other embodiments are described and claimed.

Abstract: An indication of a first performance state is received, the first performance state being associated with a first voltage. The first performance state applies to at least one computing system component and the indication is received by a computing system component distinct from the requesting computing system component. An indication of a second performance state is received. The second performance state is associated with a second voltage that is different from the first voltage. It is determined whether the second performance state is within a range defined by a minimum and maximum performance state. Responsive to a determination that the second performance state is within the minimum and maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.

Abstract: Computing system voltage control methods include receiving an indication of a first performance state. The first performance state is associated with a first voltage and applies to at least one computing system component. The indication of the first performance state is received by a first computing system component from a second computing system component. An indication of a second performance state is received, wherein the second performance state is associated with a second voltage that is not equal to the first voltage. It is determined whether the second performance state is within a range defined by a minimum performance state and a maximum performance state. Responsive to determining that the second performance state is within the range defined by the minimum performance state and the maximum performance state, the voltage of the at least one computing system component is set equal to the voltage associated with the second performance state.

Abstract: A voltage regulator may comprise a high-side switch and a low-side switch for delivering electrical current to the at least one information handling resource, a high-side driver configured to drive a high-side driving voltage for regulating a first electrical current of the high-side switch, a low-side driver configured to drive a low-side driving voltage for regulating a second electrical current of the low-side switch, and a control circuit configured to operate the at least one voltage regulator in both of a fixed dead time mode and an adaptive dead time mode.

Abstract: A distributed power management computer program product is configured to collect power consumption data that indicates power consumption by at least a plurality of the components of a node. The program code can be configured to provide, to each of a plurality of controllers associated with a respective one of the plurality of components, the power consumption data. The program code can be configured to determine a node power consumption. The program code can be configured to determine a power differential as a difference between the node power consumption and an upper power consumption threshold of the node. The program code can be configured to determine a proportion of the node power consumption consumed by a first component. The program code can be configured to compute a local power budget for the first component.