Abstract: Embodiments of the present disclosure relate to a memory system and a memory controller, in which data input/output terminals in different data input/output terminal groups corresponding to different channels may be arranged adjacent to each other, thereby preventing skew of a signal occurring during data input/output operations and interference between different signals and reducing the cost required for implementing the memory system.

Abstract: Certain embodiments described herein relate to an improved synthetic full backup image generation system. In some embodiments, one or more components in an information management system can identify a file-server-created backup copy in a particular backup format of a plurality of backup formats, determine structure information associated with the particular backup format, and generate a synthetic full backup copy according to the structure information, where the synthetic full backup copy is also in the particular backup format identical to that of the file-server-created backup copy.

Abstract: The embodiments of the present disclosure are generally directed to zero-duplicate direct-memory-access data buffer management in a data communication interface and are particularly directed to an efficient and collaborative buffer management for data transmission and synchronization between a plurality of data sources (data producers) and a data destination (data consumers) via the data communication interface. In one example, the disclosed buffer management approach combines zero-duplicate buffers, priority-based buffer allocation, priority-based data synchronization, and a collaborative communicated buffer holding time to manage the direct-memory-access and release of buffered data in a real-time and continuous dataflow producer-consumer system.

Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.

Abstract: An apparatus can include memory devices and a memory controller coupled to the memory devices via memory channels. The memory channels can disable a first memory channel associated with a first memory die in a respective memory chip of a memory device and perform a memory operation via a second memory channel involving a second memory die in the respective memory chip.

Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.

Abstract: In an embodiment, a system may support programmable hashing of address bits at a plurality of levels of granularity to map memory addresses to memory controllers and ultimately at least to memory devices. The hashing may be programmed to distribute pages of memory across the memory controllers, and consecutive blocks of the page may be mapped to physically distant memory controllers. In an embodiment, address bits may be dropped from each level of granularity, forming a compacted pipe address to save power within the memory controller. In an embodiment, a memory folding scheme may be employed to reduce the number of active memory devices and/or memory controllers in the system when the full complement of memory is not needed.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a storage area, and a controller. The controller acquires a request from a submission queue included in a host, generates one or more commands to be executed by the nonvolatile memory in accordance with the request, and stores the commands to the storage area. The controller controls throttling of acquisition of requests from the submission queue in accordance with the number of commands in the storage area and the number of requests in the submission queue.

Abstract: Described apparatuses and methods relate to erroneous select die access (SDA) detection for a memory system. A memory system may include a memory controller and a memory device that are capable of implementing an SDA protocol that enables selective memory die access to multiple memory devices that couple to a command bus. A memory device can include logic that determines if signaling that conflicts with the SDA protocol is detected. If it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. In doing so, the erroneous SDA detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.

Abstract: Techniques described herein relate to a method for performing data protection services for limited access cloud data. The method includes identifying, by a cloud service provider (CSP) proxy, a protection policy event associated with an incremental approximation backup of an object; in response to identifying the protection policy event: obtaining previous object metadata associated with the object; obtaining object data from on-premises cloud resources associated with the object; generating slices of the object data; generating current checksums and current object metadata associated with each slice; selecting a first slice of the slices; making a first determination that a first current checksum of the current checksums and a first previous checksum associated with the first slice do not match; in response to the first determination: storing the first slice in a backup storage; and updating a first portion of the current object metadata associated with the first slice.

Abstract: A method of operating a storage device includes receiving, at the storage device, a meta information transfer command based on a data read request. The meta information transfer command is received from a host device. The method further includes receiving, at the storage device, a data read command corresponding to the data read request and the meta information transfer command. The data read command is received from the host device. The method further includes receiving, at the storage device, a plurality of meta data corresponding to the data read request and the meta information transfer command. The plurality of meta data is received from the host device. The method further includes performing a data read operation, at the storage device, based on the data read command and the plurality of meta data.

Abstract: A method of processing incoming packets prior to complete reception, comprising receiving a pointer to one or more memory blocks allocated for storing one or more incoming packets to be written by one or more another controllers where each packet comprises one or more packet segments, determining all valid data values of fields contained in the packet segments. initializing one or more memory sections in the memory blocks which are mapped to the fields with predefined data pattern which are different from any of the valid values of the fields, checking continuously content of the memory sections, determining packet segment(s) were written in the memory block(s) responsive to detecting that the content of one or more of the memory sections do not match the one or more predefined data patterns, and processing one or more of the packets according to at least part of the received packet segment(s).

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract: Embodiments of the present disclosure relate to systems and methods for enabling a compute node to utilize all the resources of the cluster it is part of when accessing block storage resources. A deployment manager may receive configuration information for each of a set of compute nodes in a cluster, wherein the configuration information of each compute node in the cluster indicates a usage by the compute node of each of a set of block storage volumes (also referred to herein as storage volumes). The deployment manager determines that a first compute node cannot utilize a full amount of the storage volume bandwidth provided by one or more storage volumes assigned to it. A first storage volume of the one or more storage volumes may be reassigned to a second compute node in the cluster and deploys the cluster with the first storage volume mounted on the second compute node.

Abstract: A method for performing data access management of an all flash array (AFA) server and the AFA server operating according to the method are provided. The method includes: utilizing an upper layer program module running on a first node to detect whether any request from a client device of a user is received; in response to a write request, utilizing an intermediate layer program module to mirror data corresponding to the write request to a second node; and before the intermediate layer program module flushing the data to a lower layer program module, in response to the data being mirrored from a first volatile memory of the first node to a second volatile memory of the second node, utilizing the intermediate layer program module to send an acknowledgement to the client device without checking whether the data has been protected in any non-volatile memory of any of the multiple nodes.

Abstract: Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which solve the above problems using a global shared region of memory that combines memory segments from multiple CXL devices. Each memory segment is a same size and naturally aligned in its own physical address space. The global shared region is contiguous and naturally aligned in the virtual address space. By organizing this global shared region in this manner, a series of three tables may be used to quickly translate a virtual address in the global shared region to a physical address. This prevents TLB thrashing and improves performance of the computing system.

Abstract: A memory system including: a nonvolatile memory; first and second decoders configured to execute first and second error correction for correcting data read from the nonvolatile memory; and a controller configured to receive a first command issued by a host device, the first command being a command that requests neither reading nor writing data from or to the nonvolatile memory and that includes information indicative of acceptable latency of error correction, in response to receiving the first command, select one of the first decoder and the second decoder based on the received first command, and after receiving the first command, output data read from the nonvolatile memory through the selected one of the first decoder and the second decoder to the host device.

Abstract: Methods, systems, and devices for dynamic logical page sizes for memory devices are described. A memory device may use an initial set of logical pages each having a same size and one or more logical-to-physical (L2P) tables to map logical addresses of the logical pages to the physical addresses of corresponding physical pages. As commands are received from a host device, the memory device may dynamically split a logical page to introduce smaller logic pages if the host device accesses data in chunk sizes smaller than the size of the logical page that is split. The memory device may maintain one or more additional L2P tables for each smaller logical page size that is introduced, along with one or more pointer tables to map between L2P tables and entries for larger logical page sizes and L2P tables and entries associated with smaller logical page sizes.

Abstract: Methods, systems, and devices for address verification at a memory system are described. A memory system may determine an address identifier based on a received read command and maintain the determined address identifier in a protected state to validate a subsequent read operation. For example, the memory system may store the determined address identifier in a first memory array, separate from a second memory array that is read from in response to the read command. The memory system may also extract an address identifier from memory cells being read in response to the read command, which may include decoding or other interpreting operations performed on information read from the memory cells. The address identifier extracted from the memory cells may be compared with the address identifier determined from the read command and maintained in the protected state, which may support a determination of how to respond to the read command.

Abstract: Apparatus, methods, and software for protecting a plurality of memory locations are disclosed. Logical addresses are translated into physical addresses in dependence on one of a first translation function and a second translation function. A transitional logical address and an associated transitional value are locally held in circuitry which applies the translation functions. A remapping of first to second translation function usage is performed by determining a new transitional physical address by applying the second translation function to the transitional logical address; determining a new transitional logical address by applying an inverse of the first translation function to the new transitional physical address; retrieving a new transitional value using the new transitional physical address; storing the old transitional value to the memory location indicated by the new transitional physical address; and locally storing the new transitional value.