Patents Examined by Gary W Cygiel
  • Patent number: 11379152
    Abstract: An apparatus comprises transaction handling circuitry to issue memory access transactions, each memory access transaction specifying an epoch identifier indicative of a current epoch in which the memory access transaction is issued; transaction tracking circuitry to track, for each of at least two epochs, a number of outstanding memory access transactions issued in that epoch; barrier termination circuitry to signal completion of a barrier termination command when the transaction tracking circuitry indicates that there are no outstanding memory access transactions remaining which were issued in one or more epochs preceding a barrier point; and epoch changing circuitry to change the current epoch to a next epoch, in response to a barrier point signal representing said barrier point. This helps to reduce the circuit area overhead for tracking completion of memory access transactions preceding a barrier point.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: July 5, 2022
    Assignee: Arm Limited
    Inventors: Andrew Brookfield Swaine, Peter Andrew Riocreux
  • Patent number: 11379131
    Abstract: A memory appliance may be provided comprising a processor, a communication interface, a memory, and a region access unit. The memory may be configured in an address space addressable by the processor. The communication interface may be configured to provide the client access to the region of the memory via client-side memory access before initialization of all of the region. A method to create a virtual copy of memory accessible by client-side memory access is also provided. A system may be provided that memory maps at least a portion of a file to a memory region, wherein a virtual address addressable is generated, and the at least a portion of file is accessible through the memory region at the virtual address. The virtual address may be registered with the communication interface, where registration of the virtual address provides client-side memory access to the memory region.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 5, 2022
    Assignee: KOVE IP, LLC
    Inventors: Timothy A. Stabrawa, Zachary A. Cornelius, John Overton, Andrew S. Poling, Jesse I. Taylor
  • Patent number: 11379153
    Abstract: A processing device of a memory sub-system can monitor a plurality of received commands to identify a forced unit access command. The processing device can identify a metadata area of the memory device based on the forced unit access command. The processing device can also perform an action responsive to identifying a subsequent forced unit access command to the metadata area.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Roberto Izzi, Nicola Colella, Danilo Caraccio, Alessandro Orlando
  • Patent number: 11360694
    Abstract: Method providing resilient execution of a service on a computing device. The service is stored in a non-volatile memory of the computing device and comprises instructions executable by a processor of the computing device. The processor generates an operational instance of the service, which comprises a reference to the service. The processor stores the operational instance of the service in the non-volatile memory with a read-write access right. The processor launches an executable instance of the service associated to the operational instance of the service. The launching comprises copying the instructions of the service from the non-volatile memory to a volatile memory of the computing device. The launching further comprises executing the instructions of the service copied into the volatile memory. The processor adds data generated by the execution of the instructions of the service to the operational instance of the service for permanent storage in the non-volatile memory.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: June 14, 2022
    Assignee: DISTECH CONTROLS INC.
    Inventor: Francois Gervais
  • Patent number: 11360709
    Abstract: A gate signal control circuit of a DDR memory system includes a comparing circuit, a flag generator and a signal generator. The comparing circuit receives a first data strobe signal and a second data strobe signal, and generates an internal data strobe signal. The flag generator receives a physical layer clock signal and a read enable signal, and generates plural flag signals. The signal generator receives the internal data strobe signal and the plural flag signal, and generates a gate signal. When plural read commands are issued, the flag generator sets the flag signals according to the physical layer clock signal and the read enable signal. When a read data is received, the signal generator opens the gate signal according to a preamble, and the signal generator samples the plural flag signals to determine the timing of closing the gate signal.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: June 14, 2022
    Assignee: FARADAY TECHNOLOGY CORPORATION
    Inventors: Hong-Yi Wu, Sivaramakrishnan Subramanian, Sridhar Cheruku, Ko-Ching Chao
  • Patent number: 11360679
    Abstract: A memory appliance may be provided comprising a processor, a communication interface, a memory, and a region access unit. The memory may be configured in an address space addressable by the processor. The communication interface may be configured to provide the client access to the region of the memory via client-side memory access before initialization of all of the region. A method to create a virtual copy of memory accessible by client-side memory access is also provided. A system may be provided that memory maps at least a portion of a file to a memory region, wherein a virtual address addressable is generated, and the at least a portion of file is accessible through the memory region at the virtual address. The virtual address may be registered with the communication interface, where registration of the virtual address provides client-side memory access to the memory region.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: June 14, 2022
    Assignee: KOVE IP, LLC.
    Inventors: Timothy A. Stabrawa, Zachary A. Cornelius, John Overton, Andrew S. Poling, Jesse I. Taylor
  • Patent number: 11354050
    Abstract: Data processing method, apparatus, and mobile terminal are provided. A requesting end adds a reserved field to data to be stored to obtain target data, and sends the target data to a storing end. The storing end allocates a memory to cache the target data, generates data metadata of the data to be stored in the target data, and writes the data metadata to a memory location corresponding to the reserved field in the memory. The embodiments of the present disclosure realize zero copying, ensure the efficiency of data storage, and improve the system performance.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: June 7, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Jinxin Liu, Chengyu Dong, Shanyang Liu
  • Patent number: 11354059
    Abstract: A computer-implemented method is provided for generating a sequence of commands for replicating data on a source storage system to a destination storage system. The source and destination storage system support a first and a second remote file access protocol. The method involves i) scanning a directory of the source storage system for file system objects by the first and second remote file access protocol thereby obtaining a respective first and second representation of the file system objects; and ii) generating the sequence of commands based on the first and second representation and based on a predetermined rule set comprising rules for generating a command for replicating a file system object depending on a difference in representation of file system objects by the first and second remote file access protocol.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: June 7, 2022
    Assignee: DATADOBI CVBA
    Inventors: Kim Marivoet, Ives Aerts, Pepijn Van Eeckhoudt
  • Patent number: 11347425
    Abstract: A data mover selection system includes a memory system coupled to first and second data mover devices, and an operating system coupled to the first and second data mover devices. The operating system determines that a first data transfer operation provides for the transfer of data between first and second memory locations in the memory system, and identifies the first data mover device for performing the first data transfer operation based on the first data mover device having a higher priority relative to the second data mover device for performing data transfers between the first and second memory locations in the memory system. In response, the operating system transmits a first data transfer instruction to the first data mover device that causes the first data mover device to perform the first data transfer operation to transfer data between the first and second memory locations in the memory system.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: May 31, 2022
    Assignee: Dell Products L.P.
    Inventors: Shyam Iyer, Srinivas Giri Raju Gowda, Anh Dinh Luong
  • Patent number: 11340794
    Abstract: A system has a collection of central processing units. Each central processing unit is connected to at least one other central processing unit and has a path into flash memory resources. A central processing unit supports a mapping from a data address space, to a flash memory virtual address space, to a flash memory virtual page number to a flash memory physical address space.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 24, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mark Himelstein, James Yarbrough, Rick Carlson, Vishwas Durai, Vikram Venkataraghavan, Bruce A. Wilford, Grace Ho, Bill Katz, Richard Van Gaasbeck, Dan Arai, David R. Emberson
  • Patent number: 11340834
    Abstract: Improved scaling of an ordered event stream (OES) is disclosed. In contrast to conventional scaling of an OES that, in immediate response to loading exceeding a given processor performance level, merely divides a segment into segments having similar key space size, and then determines an alternate OES topology. The alternate OES topology can be selected from among ranked alternate OES topologies. The alternate OES topology can be implemented where the expected performance will meet a threshold level of improvement over an existing OES topology. Moreover, the alternate OES topology of the disclosed subject matter can comprise two or more two new segments that can have dissimilar key space sizes. Additionally, the two or more two new segments of the alternate OES topology can provide the same, or similar, loading relative to performance levels of corresponding processing instances, even where the performance levels of corresponding processing instances are also dissimilar.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: May 24, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Yohannes Altaye
  • Patent number: 11327677
    Abstract: An integrated circuit (IC) can include a decomposer data mover circuit configured to read sub-arrays from array data stored in a source memory; generate metadata headers for the sub-arrays, wherein each metadata header includes location information indicating location of a corresponding sub-array within the array data; create data tiles, wherein each data tile includes a sub-array and a corresponding metadata header; and output the data tiles to compute circuitry within the IC. The IC can include a composer data mover circuit configured to receive processed versions of the data tiles from the compute circuitry; extract valid data regions from the processed versions of the data tiles; and write the valid data regions to a destination memory based on the location information from the metadata headers of the processed versions of the data tiles.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: May 10, 2022
    Assignee: Xilinx, Inc.
    Inventors: Kristof Denolf, Jack S. Lo, Kornelis A. Vissers
  • Patent number: 11321007
    Abstract: Storing data volumes in virtual and physical address spaces such that the data units are contiguous in virtual address space but fragmented in physical address space. The mapping between virtual and physical address space is managed by a storage controller that is configured to implement deletes reversibly with a so-called soft delete, the soft delete being reversible up to a later permanent or hard delete. A soft delete triggers a compaction in which the data units of the to-be-deleted volume are gathered together in physical address space. During the time between compaction and hard delete (or restore), the soft deleted volume is thus stored in a space efficient manner. Moreover, the subsequent hard delete can be performed more quickly than if the soft deleted volume were still fragmented across physical address space freeing up space quicker.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Paul Nicholas Cashman, Gemma Izen, Ben Sasson
  • Patent number: 11314453
    Abstract: A memory system includes: a memory device including: a first memory block storing first map data, which maps a first logical address to a first physical address; and a second memory block storing first user data corresponding to the first map data; and a controller configured to: receive a warning signal from a host; and back up the first map data as second map data in response to the first logical address being provided along with a write command received after the warning signal is received; update the first map data to map the first logical address to a second physical address; suspend an erase operation being performed on the first user data is invalidated due to the write command; and restore the first map data based on the second map data and validate the invalidated first user data when it is determined that the host is infected by malware.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: April 26, 2022
    Assignee: SK hynix Inc.
    Inventors: Jong-Pil Jung, Duck-Hoi Koo
  • Patent number: 11314450
    Abstract: A method of operating a storage device includes receiving, at the storage device, a meta information transfer command based on a data read request. The meta information transfer command is received from a host device. The method further includes receiving, at the storage device, a data read command corresponding to the data read request and the meta information transfer command. The data read command is received from the host device. The method further includes receiving, at the storage device, a plurality of meta data corresponding to the data read request and the meta information transfer command. The plurality of meta data is received from the host device. The method further includes performing a data read operation, at the storage device, based on the data read command and the plurality of meta data.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-Woo Kim, Dong-Min Kim, Song-Ho Yoon, Wook-Han Jeong
  • Patent number: 11314656
    Abstract: Systems and methods for processing memory address spaces corresponding to a shared memory are disclosed. After a writer restart process, pre-restart writer pointers of a pre-restart writer addressable space in the shared memory are replaced with corresponding location independent pointers. A writer pointer translation table is rebuilt in the shared memory to replace an association of modified pre-restart writer pointers and pre-restart translation base pointers based on the pre-restart writer pointers, respectively, with an association of modified post-restart writer pointers and post-restart translation base pointers based on post-restart writer pointers, respectively. After the writer pointer translation table is rebuilt, the location independent pointers are replaced with post-restart writer pointers in the shared memory, respectively, and the post-restart writer pointers are stored in the shared memory for access by one or more readers of the shared memory.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: April 26, 2022
    Assignee: ARISTA NETWORKS, INC.
    Inventors: Duncan Stuart Ritchie, Christopher Elisha Neilson, Sebastian Sapa
  • Patent number: 11314454
    Abstract: In a method for accessing a storage system, a client in the storage system identifies a logical address of a storage device, and queries a management server regarding a mapping between the storage device and a start address of a submission queue (SQ) in the memory of the storage node. The client then sends an access request including the logical address of the storage device directed to the start address of the SQ to a network interface card NIC of the storage node. The NIC receives and sends the access request to the start address of the SQ in the memory. The storage device obtains the access request from the start address of the SQ and executes the access request.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: April 26, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Dan Luo, Yu Liu, Wei Zhang, Wei Mao
  • Patent number: 11244729
    Abstract: A memory device to search for a voltage optimized to read a group of memory cells. In response to a read command, the memory device measures first signal and noise characteristics of the memory cells by reading the memory cells at first test voltages. Based on the first signal and noise characteristics, the memory device may determine that the optimized read voltage is outside of a range of the first test voltages. In response, the memory device determines, based on the first signal and noise characteristics, an estimate of the optimized read voltage, and measures second signal and noise characteristics by reading at second test voltages configured around the estimate. The optimized read voltage can be computed based at least in part on the second signal and noise characteristics. The memory device retrieves data from the memory cells using the optimized read voltage.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Patrick Robert Khayat, James Fitzpatrick, AbdelHakim S. Alhussien, Sivagnanam Parthasarathy
  • Patent number: 11232041
    Abstract: An example apparatus for memory addressing can include an array of memory cells. The apparatus can include a memory cache configured to store at least a portion of an address mapping table. The address mapping table can include a number of regions corresponding to respective amounts of logical address space of the array. The address mapping table can map translation units (TUs) to physical locations in the array. Each one of the number of regions can include a first table. The first table can include entries corresponding to respective TU logical address of the respective amounts of logical address space, respective pointers, and respective offsets. Each one of the number of regions can include a second table. The second table can include entries corresponding to respective physical address ranges of the array. The entries of the second table can include respective physical address fields and corresponding respective count fields.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: January 25, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Jonathan M. Haswell
  • Patent number: 11221795
    Abstract: Methods, systems, and computer program products for queue management are provided. Aspects include receiving a first queue entry and storing the first queue entry in a queue at a first location, wherein the first queue entry includes a first target destination, receiving a second queue entry and storing the second queue entry in the queue at a second location, wherein the second queue entry includes a second target destination, tracking a relative age for each of the first queue entry and the second queue entry, transmitting the first queue entry to the first target destination based at least in part on the relative age for the first queue entry being greater than the relative age for the second queue entry, and receiving a third queue entry and storing the third queue entry in the queue at the first location.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary E. Strait, Matthias Klein, Alia Shah, Sajay Mathew Karottukottarathil Baby