Abstract: The invention relates to a method for coordinating an execution of an instruction sequence by a processor device of a coherent shared memory system. An instruction is executed and causes the processor device to fill a copy of a memory line to a processor cache memory. The memory line is flagged by the processor device upon detection of first flag information which indicates that propagation of memory coherence across the shared memory system in respect of the memory line is unconfirmed. The memory line is unflagged by the processor device upon detection of second flag information which indicates that the propagation of memory coherence in respect of the memory line is confirmed. Upon execution of a memory barrier instruction, a completion of execution of the memory barrier instruction is prevented while the memory line is flagged.

Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.

Abstract: An example apparatus for die addressing can include an array of memory cells and a memory cache. The memory cache can be configured to store at least a portion of an address mapping table. The address mapping table can include entries that map translation units (TUs) to physical locations in the array. The entries can include data that indicate a location within the array that stores a particular TU without including data that indicates which die of the array the TU is stored in.

Abstract: The present disclosure describes data transfer in a memory device from sensing circuitry to controller. An example apparatus includes a controller coupled to a memory device. The controller is configured to execute a command to transfer data from a latch component to a register file in the controller. The memory device includes an array of memory cells and the latch component is coupled to rows of the array via a plurality of columns of the memory cells. The latch component includes a latch selectably coupled to each of the columns and configured to implement the command to transfer the data. The memory device includes a data line to couple the latch component to the register file to transfer the data. The controller is configured to couple to the data line and the register file to perform a write operation on the transferred data to the register file in the controller.

Abstract: According to one or more embodiments of the present invention, computer implemented method includes obtaining by an input/output (I/O) subsystem a request block that includes a command code indicating a STORE IOP-UTILIZATION DATA command for tracking resource utilization during an asynchronous execution of an instance of a CPU DEFLATE command. The method further includes, based on the command code, initiating a command response block. The command response block includes multiple entries for input/output processor (IOP) utilization, each entry corresponding to resource utilization measurements of each IOP in the I/O subsystem. The method further includes, storing, in a command response code field of the command response block, a response code indicating that the resource utilization measurements have been recorded in the entries for IOP utilization. The response block includes a length code indicating a length of the response block and the response code field.

Abstract: Method and apparatus for handling page protection faults in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. In one exemplary aspect, a page protection fault handling unit is used to detect memory accesses, to check page protection information relevant to the detected access by examining the contents of a page descriptor store, and to selectively allow the access or pass on page protection fault information in accordance with the page protection information.

Abstract: Controlling a rate of prefetching based on bus bandwidth. A determination is made as to whether a rate of prefetching data from memory into a cache is to be changed. This determination is based on bus utilization, and includes identifying a most utilized bus of a plurality of buses used for the prefetch of data, and monitoring utilization of the most utilized bus. The determination whether the rate of prefetching is to be changed is based on the monitoring. Based on determining that the rate is to be changed, the rate of prefetching is changed.

Abstract: A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system also includes one or more processing units that each include a plurality of compute units for concurrently executing work-groups of work items, a plurality of second caches associated with the plurality of compute units and configured in a hierarchy with the one or more first caches, and a plurality of second lock tables associated with the plurality of second caches. The first and second lock tables indicate locking states of addresses of cache lines in the corresponding first and second caches on a per-line basis.

Abstract: An NAND flash memory and a reading method thereof capable of high-speed reading of SFDP data are provided. The flash memory includes a memory cell array, a page buffer/reading circuit 170 and a controller 150. The page buffer/reading circuit 170 includes a first latch circuit L1 and a second latch circuit L2. The first latch circuit L1 keeps data read from the memory cell array. The second latch circuit L2 keeps data transferred from the first latch circuit L1. Just after power is turned on or reset, the controller 150 controls data of block 0/page 0 of the memory cell array to be kept in the second latch circuit L2 and controls the SFDP data to be kept in the first latch circuit L1. The SFDP data or the data of block 0/page 0 is serially output according to an input command.

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing memories by overlapping ranges of pages in nonvolatile memory systems are provided. An example memory system includes a memory controller coupled to a memory and configured to: determine a range of logical addresses associated with a command, search particular mapping tables including the range of logical addresses in mapping pages in the memory, determine whether a starting address of the range of logical addresses is in an overlapped range of first and second sequential mapping pages, the overlapped range including logical addresses of one or more mapping tables duplicated in the first and second mapping pages, determine which of the first and second mapping pages from which the particular mapping tables to be loaded based on a result of determining whether the starting address is in the overlapped range, and load the particular mapping tables from the determined mapping page.

Abstract: Methods and apparatus are provided for reporting fragment filling in storage systems. An exemplary method comprises obtaining at least one compressed allocation unit of data in a storage system; reserving space for the at least one compressed allocation unit in a compressed segment based on a greater of (i) a size of the at least one compressed allocation unit, and (ii) a minimum target fragment length specified for at least one write operation class; and writing the at least one compressed allocation unit to the reserved space. An attempt is optionally first made to fill the at least one compressed allocation unit of data in a free extent and/or a hidden fragment of at least one compressed segment prior to reserving the space. The reserving the space is optionally only performed if the attempt to fill the at least one compressed allocation unit of data is not successful.

Abstract: A method, computer program product, and computer system for forming, by a computing device, one or more virtual storage arrays using one or more storage processor virtual machines. A storage stack may be run inside the one or more storage processor virtual machines. One or more storage device drives of the one or more virtual storage arrays may be simulated as files.

Abstract: Systems and techniques for bi-directional negotiation for dynamic data chunking are described herein. A set of available features for a memory subsystem. The set of available features including latency of buffer locations of the memory subsystem. An indication of a first latency requirement of a first data consumer and a second latency requirement of a second data consumer may be obtained. A first buffer location of the memory subsystem for a data stream based on the first latency requirement may be negotiated with the first data consumer. A second buffer location of the memory subsystem for the data stream based on the second latency requirement may be negotiated with the second data consumer. An indication of the first buffer location may be provided to the first data consumer and an indication of the second buffer location may be provided to the second data consumer.

Abstract: Dynamically provisionable and allocatable memory external to a requesting apparatus may be provided. A request for primary memory may be made by an application executing on a client. An allocation logic unit may determine an allocation strategy in response to the request. As part of the allocation strategy, the allocation logic unit may identify memory appliances on which memory regions are to be allocated. The allocated memory regions may form the primary memory that is allocated to the requesting application. The allocation logic unit may send region allocation requests to region access unit of the respective memory appliances. The memory appliances on which the memory regions are allocated may be external to the client. The application may access the allocated memory regions via client-side access in which one or more processors in the client and/or the memory appliances are bypassed.

Abstract: Technology for a memory controller is described. The memory controller can receive a request to store training data. The request can include a model identifier (ID) that identifies a model that is associated with the training data. The memory controller can send a write request to store the training data associated with the model ID in a memory region in a pooled memory that is allocated for the model ID. The training data that is stored in the memory region in the pooled memory can be addressable based on the model ID.

Abstract: At least one address scheduling method includes selecting a first bit line, selecting a first string connected to the first bit line, performing address scheduling on N pages of each of multi-level cells in the first string sequentially from a bottom word line to a top word line, and after completing the address scheduling on all word lines in the first string, performing address scheduling on second to k-th strings sequentially in the same manner as performed with respect to the first string, where “k” is 2 or a natural number greater than 2.

Abstract: A memory system includes a memory controller configured to generate a memory control signal for controlling a read operation or a write operation of data, and a plurality of memory devices configured to perform the read operation or the write operation in response to the memory control signal. A first memory device stores a first number of data received from the memory controller, and a second memory device receives a second number of data corresponding to a specific number of data from among the first number of data, copies the second number of data to generate a third number of data, and stores the third number of data in the second memory device.

Abstract: Dynamically allocating cache in a multi-tenant infrastructure includes monitoring cache usage for multiple workloads in a multi-tenant processing infrastructure to determine a workload phase. A baseline performance level per workload is determined. The baseline performance level is dependent upon the workload phase. The workloads for each tenant are categorized based on cache utilization and the cache is allocated to each workload based on the baseline performance level, cache utilization, and system wide cache capacity.

Abstract: Disclosed herein are system, method, and computer program product embodiments for cache partitioning to accelerate concurrent workload performance of in-memory databases. An embodiment operates by storing a first bitmask, associating the first bitmask with a first processor core, setting a subset of the bits of the first bitmask, wherein the subset of the bits of the first bitmask represents a first portion of shared last-level cache, and wherein any part of the first bitmask excluding the subset of the bits of the first bitmask represents a second portion of the lowest-level cache, and disallowing eviction of any cache line in the second portion of the lowest-level cache by the first processor core.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller which controls the nonvolatile memory. The controller notifies to an outside an extensive signal which indicates a predetermined state of the nonvolatile memory or the controller.