Abstract: A technique capable of realizing a semiconductor gas sensor having a high rising response speed is provided. A gate insulating film (e.g., a SiO2 film) is formed on a Si layer, and a modified TiOx (a TiOx nanocrystal) film is formed on the gate insulating film. Further, on the modified TiOx film, a Pt film is formed. This Pt film is composed of a plurality of Pt crystal grains, and in a crystal grain boundary gap existing among the plurality of Pt crystal grains, Ti and oxygen (O) are present, and particularly, a TiOx nanocrystal is formed on a surface in the vicinity of a grain boundary triple point as the center.

Abstract: Methods of fabricating interconnection structures of a semiconductor device are provided. The method includes, inter alia: forming a first insulation layer on a semiconductor substrate, forming a mold layer having trenches on the first insulation layer, forming a sidewall protection layer including a first metal silicide layer on sidewalls of the trenches, forming second metal lines that fill the trenches, forming upper protection layers on the second metal lines, removing the mold layer after formation of the upper protection layers to provide gaps between second metal lines, and forming a second insulation layer in the gaps and on the upper protection layers. The second insulation layer is formed to include air gaps between the second metal lines. Related interconnection structures are also provided.

Abstract: A semiconductor configuration, which includes an epitaxial layer of the first conductivity type disposed on a highly doped substrate of first conductivity type; a layer of a second conductivity type introduced into the epitaxial layer; and a highly doped layer of the second conductivity type provided at the surface of the layer of the second conductivity type. Between the layer of the second conductivity type and the highly doped substrate of the first conductivity type, a plurality of Schottky contacts, which are in the floating state, are provided mutually in parallel in the area of the epitaxial layer.

Abstract: Method, algorithms, architectures, packages, circuits, and/or approaches for relatively low cost packaged integrated circuits (e.g., ball grid array or BGA packages) are disclosed. For example, a packaged integrated circuit can include a first chip, the first chip including a plurality of bond pads; a plurality of bond pad connectors in electrical communication with the plurality of bond pads; a substrate having a plurality of layers, at least one of the plurality of layers being configured to electrically connect the plurality of bond pad connectors and a plurality of external package connections; and a redistribution layer on the first chip, wherein the redistribution layer is configured to electrically connect at least one of the plurality of bond pad connectors and at least one of the plurality of bond pads on the first chip.

Abstract: A semiconductor device according to an embodiment has: a semiconductor substrate; an acoustic resonator formed on the semiconductor substrate, having a semiconductor layer including impurity electrically isolated from the substrate by depletion layer and configured to resonate at a predetermined resonance frequency based on acoustic standing wave excited in the semiconductor layer; a temperature detector formed on the semiconductor substrate and configured to detect temperature of the semiconductor substrate; a calculating unit formed on the semiconductor substrate and configured to perform calculation of temperature compensation based on the temperature detected by the temperature detector, kind of the impurity and concentration of the impurity; and a controller formed on the semiconductor substrate and configured to control the resonance frequency based on a result of the calculation by the calculating unit.

Abstract: A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

Abstract: The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting these wafers to a heat treatment under an oxidizing atmosphere to bond the wafers together; grinding and removing the outer periphery of the bond wafer so that the outer periphery has a predetermined thickness; subsequently removing an unbonded portion of the outer periphery of the bond wafer by etching; and then thinning the bond wafer so that the bond wafer has a desired thickness, wherein the etching is conducted by using a mixed acid at 30° C. or less at least comprising hydrofluoric acid, nitric acid, and acetic acid.

Abstract: A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

Abstract: The present invention relates to a LED module which converts pump light from a LED chip (120) to light at another wavelength, which is emitted from the module. The conversion takes place in a portion of a luminescent material (124). The color purity of the LED module is enhanced by reducing any leakage of pump light using a reflector in combination with an absorber. In one embodiment, the absorber is integrated as one or several thin absorbing layers between the layers of a multi-layer reflection filter (126); this may yield an even higher reduction of pump light leakage from the module.

Abstract: A liquid-filled light emitting diode (LED) bulb including a base, a shell, one or more LEDs, a thermally conductive liquid, and a bladder. The shell is connected to the base and the thermally conductive liquid is held within the shell. The one or more LEDs are disposed within the shell and immersed in the thermally conductive liquid. The bladder is also immersed in the thermally conductive liquid and is configured to compensate for expansion of the thermally conductive liquid.

Abstract: A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the semiconductor layer and the substrate are covered by the first dielectric layer. The first conductive layer is formed on a part of the first dielectric layer. The second dielectric layer is formed on the first conductive layer, and the lateral side of the stacking structure including the second dielectric layer and the first conductive layer has a taper shaped. The second conductive layer is formed on a part of the second dielectric layer.

Abstract: A solid-state imaging device includes a substrate with oppositely facing first surface and second surfaces, light being received through the second surface; a wiring layer on the first surface; a photodetector in the substrate; a charge accumulation region between the second surface and the photodetector; and an insulating layer over the second surface, the insulating layer have a region that is at least partially crystallized.

Abstract: A multigate structure which comprises a semiconductor substrate; an ultra-thin silicon or carbon bodies of less than 20 nanometers thick located on the substrate; an electrolessly deposited metallic layer selectively located on the side surfaces and top surfaces of the ultra-thin silicon or carbon bodies and selectively located on top of the multigate structures to make electrical contact with the ultra-thin silicon or carbon bodies and to minimize parasitic resistance, and wherein the ultra-thin silicon or carbon bodies and metallic layer located thereon form source and drain regions is provided along with a process to fabricate the structure.

Abstract: A pixel, a storage capacitor, and a method for forming the same. The storage capacitor formed on a substrate comprises a semiconductor layer, a first dielectric layer, a first conductive layer, a second dielectric layer and a second conductive layer. The semiconductor layer is formed on the substrate wherein the semiconductor layer and the substrate are covered by the first dielectric layer. The first conductive layer is formed on a part of the first dielectric layer. The second dielectric layer is formed on the first conductive layer, and the lateral side of the stacking structure including the second dielectric layer and the first conductive layer has a taper shaped. The second conductive layer is formed on a part of the second dielectric layer.

Abstract: A semiconductor processing method to provide a high quality bottom oxide layer and top oxide layer in a charged-trapping NAND and NOR flash memory. Both the bottom oxide layer and the top oxide layer of NAND and NOR flash memory determines array device performance and reliability. The method describes overcomes the corner thinning issue and the poor top oxide quality that results from the traditional oxidation approach of using pre-deposited silicon-rich nitride.

Abstract: A chip contact pad and a method of making a chip contact pad are disclosed. An embodiment of the present invention includes forming a plurality of contact pads over a workpiece, each contact pad having lower sidewalls and upper sidewalls and reducing a lower width of each contact pad so that an upper width of each contact pad is larger than the lower width. The method further includes forming a photoresist over the plurality of contact pads and removing portions of the photoresist thereby forming sidewall spacers along the lower sidewalls.

Abstract: After forming a pressure-bonded ball and a ball neck by bonding an initial ball to a pad, a capillary is moved upward, away from a lead, and then downward, thereby the ball neck is trodden on by a face portion that is on the lead side of the capillary. Subsequently, the capillary is moved upward and then toward the lead until the face portion of the capillary is positioned above the ball neck, thereby a wire is folded back toward the lead. Then, the capillary is moved downward such that a side of the wire is pressed by the capillary against the ball neck that has been trodden on. After the capillary is moved obliquely upward toward the lead and then looped toward the lead, the wire is pressure-bonded to the lead.

Abstract: This photodetector capable of detecting electromagnetic radiation comprises: a doped semiconductor absorption layer for said radiation, capable of converting said radiation into charge carriers; a reflective layer that reflects the incident radiation that is not absorbed by semiconductor layer towards the latter, located underneath semiconductor layer; and a metallic structure placed on semiconductor layer that forms, with semiconductor layer, a surface Plasmon resonator so as to concentrate the incident electromagnetic radiation on metallic structure in the field concentration zones of semiconductor layer. Semiconductor zones for collecting charge carriers that are oppositely doped to the doping of semiconductor layer are formed in said semiconductor layer and have a topology that complements that of the field concentration zones.

Abstract: Provided are three-dimensional semiconductor memory devices and methods of forming the same. The device includes a substrate, conductive patterns stacked on the substrate, and an active pattern penetrating the conductive patterns to be connected to the substrate. The active pattern may include a first doped region provided in an upper portion of the active pattern, and a diffusion-resistant doped region overlapped with at least a portion of the first doped region. The diffusion-resistant doped region may be a region doped with carbon.

Abstract: This photodetector comprises a doped semiconductor layer; a reflective layer located underneath semiconductor layer; a metallic structure placed on semiconductor layer that forms, with semiconductor layer, a surface plasmon resonator, a plurality of semiconductor zones formed in semiconductor layer and oppositely doped to the doping of the semiconductor layer; and for each semiconductor zone, a conductor that passes through the photodetector from reflective layer to at least semiconductor zone and is electrically insulated from metallic structure, with semiconductor zone associated with corresponding conductor thus determining an elementary detection surface of the photodetector.