Abstract: A fully amorphous thin film material that is related to ferroelectric compositions which is grown at low temperature, e.g., below 400° C., to yield a material with voltage independent capacitance, capacitance density of from about 1000 to about 10000 nF/cm2, leakage of <10−7 A/cm2, root mean square roughness <1 nanometer independent of film thickness, and an inverse capacitance that scales as a ratio of film thickness, reflecting uniform dielectric constant throughout the film. The film material may be employed for various capacitor structures, including decoupling capacitors, DRAM storage capacitors, feedthrough capacitors, bypass capacitors, capacitors for RC filters and capacitors for switched capacitor filters.

Abstract: An MIS transistor fabricated in a manner that minimizes the occurrence of leak currents and that improves overall transistor performance by minimizing variation in location of the transistor source and drain during fabrication thereof. A gate electrode is first fabricated on a substrate. Next, a thermal oxide layer is formed on a side of the gate electrode. A masking process is then performed with the thermal oxide layer to form a source and a drain. A silicon oxide layer is then deposited over the gate electrode, the source and the drain. An etching process is performed on the silicon oxide to form a side wall oxide film over the thermal oxide layer on the side of the gate electrode and to expose surfaces of the gate electrode, the source and the drain. A metal film is then deposited over the gate electrode, the source and the drain and is heat treated to form a metal silicide film on the exposed surfaces of the gate electrode, the source and the drain.

Abstract: The semiconductor device comprises a MOSFET including a pair of impurity diffused regions formed on both sides of a gate formed on a semiconductor substrate; an insulation film covering a top of the MOSFET and having a through-hole opened on one of the impurity diffused regions formed in; and a capacitor formed at least a part of an inside of the through-hole, the through-hole having a larger diameter inside than at a surface thereof or having a larger diameter at an intermediate part between the surface thereof and a bottom thereof than the surface and the bottom thereof.

Abstract: A nonvolatile semiconductor memory device includes a silicon substrate, a floating gate electrode formed on silicon substrate with a silicon oxide film therebetween, a control gate electrode formed on a portion of floating gate electrode with an interlayer insulating film therebetween, and an erase electrode formed on another portion of floating gate electrode with an insulating film therebetween. The insulating film includes a silicon nitride film and a silicon oxide film.

Abstract: A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

Abstract: A non-volatile memory cell, comprising a semiconductor substrate having a first conductivity type. A control region is formed of said first conductivity type in the substrate and a control region oxide formed over the control region. The cell includes a program element having a first active region of a second conductivity type formed in said substrate, a doped or implanted region adjacent to said first active region, and a gate oxide overlying at least the channel region. An active region oxide covers a portion of the first active region. A floating gate is formed over said semiconductor substrate on said active region oxide and said control region oxide.

Abstract: A method for forming a semiconductor device with a doped channel-region, and the device formed therefrom. In one embodiment, the method invention is comprised of two principal steps. The first step is to provide a semiconductor substrate to which the following process steps can be performed. The second step is to create a doping profile into the channel-region of the semiconductor substrate. The doping profile is created by a) performing a first doping implantation with a first dopant in a first concentration to a first depth within the semiconductor substrate, and b) performing a second doping implantation with a second dopant in a second concentration to a second depth within the semiconductor substrate.

Abstract: Embodiments of the invention comprise a new device and technique to realize an improved coupling ratio integrated circuit device. This improvement is achieved by increasing an overlap portion between the first and second polysilicon layers, so as to increase the effective coupling ratio between the layers. In the embodiments of the present invention, a relatively tall or large portion of oxide is formed over at least a portion of each of a plurality of shallow trench isolation regions. This oxide is then utilized to provide a larger first polysilicon layer surface area, but without substantially increasing the tunnel oxide layer surface area. Then, a dielectric interlayer is formed upon the surface of the first polysilicon layer, and next, a second polysilicon layer is formed upon the dielectric interlayer. This increased overlap portion thus allows for an increased coupling ratio.

Abstract: A semiconductor device has a semiconductor substrate having a peripheral circuit area and a memory cell area. A border region having a well of a first conductivity is formed between the peripheral circuit area and the memory cell area. A well of a second conductivity is formed in the peripheral circuit area. The well in the peripheral circuit area is in contact with the border region but not in contact with the memory cell area. Dummy transistors are formed in the border region. The dummy transistors are arranged with substantially the same transistor forming density as that of the memory cell area.

Abstract: A capacitive element structure in a semiconductor device having an interconnection structure. The capacitive element structure includes a capacitive element having a capacitive dielectric film made of an oxide compound. The capacitive element structure is above at least a first level interconnection of the interconnection structure.

Abstract: The invention proposes a simple method to lower the threshold voltage of UV erased EPROM and OTP memories. During the erasure, a voltage is applied to the control gate (10) or wordline (2) which is on-chip generated as a photovoltage by means of photodiode (12) irradiated by radiation (15) during erasure. Because the wordlines are coupled to further zones forming photosensitive pn-junctions in the semiconductor body, measures are taken to prevent that, due to charge transport across said junctions, the generated photovoltage is decreased too strongly.

Abstract: A transistor of a second conductivity type is of an LMOS structure, and a transistor of a first conductivity type is of an LDMOS structure. The transistor of the first conductivity type has a drain base layer which functions in the same manner as a drain offset diffusion layer and is formed in a substrate separately from a source base diffusion layer. The transistor of the first conductivity type has a stably high breakdown voltage and a low on-state resistance as with the transistor of the second conductivity type.

Abstract: A split gate memory cell is described which is fabricated from two-polysilicon layers and comprises a silicon substrate having a source and a drain electrode and a storage node, a tunnel oxide on the substrate, a first control gate electrode and a floating gate electrode spaced from each other and fabricated from the same polysilicon layer and a second control gate electrode of a second poly material formed between and over the first control gate and floating gate and isolated therefrom by a dielectric layer therebetween.

Abstract: A novel method of forming a first polysilicon gate tip (poly-tip) for enhanced F—N tunneling in split-gate flash memory cells is disclosed. The poly-tip is formed in the absence of using a thick polysilicon layer as the floating gate. This is made possible by forming an oxide layer over the poly-gate and oxidizing the sidewalls of the polygate. Because the starting thickness of polysilicon of the floating gate is relatively thin, the resulting gate beak, or poly-tip, is also necessarily thin and sharp. This method, therefore, circumvents the problem of oxide thinning encountered in scaling down devices of the ultra large scale integration technology and the fast programmability and erasure performance of EEPROMs is improved.

Abstract: An MIS device (20) includes a semiconducting substrate (22), a silicon nitride buffer layer (24), a ferroelectric metal oxide superlattice material (26), and a noble metal top electrode (28). The layered superlattice material (26) is preferably a strontium bismuth tantalate, strontium bismuth niobate, or strontium bismuth niobium tantalate. The device is constructed according to a preferred method that includes forming the silicon nitride on the semiconducting substrate prior to deposition of the layered superlattice material. The layered superlattice material is preferably deposited using liquid polyoxyalkylated metal organic precursors that spontaneously generate a layered superlattice upon heating of the precursor solution. UV exposure during drying of the precursor liquid imparts a C-axis orientation to the final crystal, and results in improved thin-film electrical properties.

Abstract: An improved anti-fuse structure is formed on a silicon substrate of a first conductivity type. The anti-fuse has a first conductive layer formed on a surface of substrate, a dielectric layer formed on the first conductive layer, and a second conductive layer formed on the dielectric layer. The second conductive layer has a portion extending beyond the dielectric layer above the surface of the substrate. A third conductive layer is contacted to this portion of the second dielectric layer. The anti-fuse further includes a well region having a graded doping profile formed in the silicon substrate under the portion of the second conductive layer to which the third conductive layer is contacted. The well region has a second conductivity type that is opposite the first conductivity type.

Abstract: A semiconductor device having reliable electrode contacts. First, an interlayer dielectric film is formed from a resinous material. Then, window holes are formed. The interlayer dielectric film is recessed by oxygen plasma. This gives rise to tapering window holes. This makes it easy to make contacts even if the circuit pattern is complex.

Abstract: A method and structure for textured surfaces in non volatile floating gate tunneling oxide (FLOTOX) devices, e.g. FLOTOX transistors, are provided. The present invention capitalizes on using “self-structured masks” and a controlled etch to form nanometer scale microtip arrays to form the textured surfaces. The present invention further employs atomic layer epitaxy (ALE) to create a very conformal tunnel oxide layer which complements the nanometer scale microtip arrays. The resulting structure provides a higher tunneling current than currently exists in FLOTOX technology. The improved tunneling currents at low voltages can make these FLOTOX devices suitable for replacing DRAMS.

Abstract: The present invention provides a static random-access memory (SRAM) device that comprises a substrate having an insulator and a gate formed thereover, where the insulator electrically insulates the gate from the substrate, and a local conductive layer that is formed on the gate structure and that extends from the gate and onto the substrate. The local conductive layer is connectable to a conductive interconnect structure to connect the gate electrically to an other portion of the SRAM device. The SRAM device, in one embodiment, is part of a complementary metal oxide semiconductor (CMOS). However, it will be appreciated by those who are of ordinary skill the art that the present invention may be used in various types of metal oxide semiconductors and similar semiconductor devices in general.

Abstract: In a trench-gated MOSFET, a lightly doped drift region of the N-type drain lies in the mesa between the trenches. The gate is doped with N-type material so that depletion regions are formed in the drift region when the gate voltage is equal to zero. The depletion regions merge at the center of the mesa, pinching off the flow of current when the device is turned off. This current-pinching effect allows the P-type body region to be made shallower and doped more lightly than usual without creating a punchthrough problem, because the barrier represented by the depletion regions adds to the normal current blocking capability of the PN junction between the body and drain regions. When the device is turned on by biasing the gate to a positive voltage, a low resistance accumulation layer forms in the drift region adjacent the trenches.