Abstract: A register management system has more physical registers for general purpose use than are named in the architectural system. A renaming system identifies particular physical registers to perform as architected addressable or general purpose registers. An array control list (ACL) is provided to monitor the assignment and status of the physical registers. A decode register assignment list (DRAL) is provided to monitor the status of all of the architected registers and the correspondence to physical registers. A back-up register assignment list (BRAL) is used to preserve old status information while out of sequence and conditional branch instructions are executed. The physical registers may retain multiple copies of individual addressable registers representing the contents at different stages of execution. The addressable register status may be restored if instruction execution is out of sequence or on a conditional branch causing a problem requiring restoration.

Abstract: A computer system with read-only memory and permanent read/write memory provides the user with the capability of loading an alternate operating system at the conclusion of a session without turning the computer off and then on. A customization word with a system request (SR) bit is located in read/write memory and is set by routines located in ROM upon user request. A reinitialization is then forced which resets the SR bit and brings up the machine in the alternate operating system located in external memory on a diskette or fixed disk. A flexible initialization system is also disclosed providing customized initialization in a variety of operating systems and applications. The preferred customized initialization is maintained for future system start-ups due to the resetting of the SR bit.

Abstract: A method for storing and accessing data in the operation of a program driven computer system for carrying out an industrial process, which system includes a non-volatile, long access time memory medium and a volatile, short access time memory medium, which method includes: configuring the non-volatile and volatile memory media into a unitary, relational database composed of a plurality of tables each composed of an ordered set of data elements; storing in the non-volatile memory medium a set of data elements which forms at least a first table of the database and which is required by the process infrequently and/or need not be accessed rapidly; storing in the volatile memory medium a set of data elements which forms at least a second table of the database which must be rapidly accessed; executing a plurality of programs in cooperation with data elements forming the database in order to control the process; and establishing communication between the programs and the database via an interface which causes the pr

Abstract: An information processing system includes a first data processing device 10 and a second data processing device 12 each of which is capable if independent instruction execution during instruction cycles having a period which is a multiple of a periodic unit clock signal period. The devices are disclosed to be an arithmetic unit and a central processor which are coupled together by an interface 14. Each of the data processing devices include a clock generation device 180 having an input coupled to the unit clock signal for generating an associated instruction cycle clock signal which has a period which is a multiple of the unit clock signal period. The clock generation device is further operable for suspending the generation of the instruction cycle clock signal and for beginning a next instruction cycle clock signal in synchronism with a transition of the unit clock signal.

Abstract: A printed circuit board card adapted to fit into a slot and make electrical connections with cooperating terminals in the slot, the slot being disposed on the main circuit board of a personal computer system, the main circuit board including a CPU, memory, a 32-bit address bus with control signals associated therewith, and input/output circuity. The slot is coupled to the 32-bit address bus, being substantially a NUBUS bus, and the slot includes distinct identification line means which provide the slot with an identification number (distinct number) in the computer system. The card includes a decoder means which is coupled to the slot to receive the identification number; the decoder means has memory reservation means which causes 256 megabytes of memory space to be reserved for the card in the slot, such that, where the slot number is X, the 256 megabytes of reserved memory space begins at location $X000 0000 and ends at location $XFFF FFFF.

Abstract: A direct memory access (DMA) controller is adaptable to control a DMA which is independently made in a plurality of channels of a data processing apparatus, where the plurality of channels have predetermined priority sequences and the DMA controller includes a bus and terminal controller coupled to a system bus for obtaining a right to use the system bus responsive to a transfer request, an interrupt and slave controller coupled to the system bus for controlling an interrupt which is made to a central processing unit (CPU) when a data transfer ends for each of the plurality of channels and for controlling an access from the CPU, and an operation determination part for determining an operation of the DMA controller depending on the transfer request, whether or not the bus and terminal controller obtained the right to use the system bus and whether or not the access is made from the CPU.

Abstract: An input device, in particular for a medical monitoring system, comprises a keyboard, a screen and a control processor. The keyboard comprises various hardkeys enabling access to an object mode in which the user may enter an object to be manipulated. Once an object is selected, the device enters a task/action mode in which the user may define an action to be performed on the selected object.

Abstract: A reduced instruction set type microprocessor which reduces loss of central processing unit (CPU) time. A circuit is provided to identify and keep track of whether an arithmetic instruction requires operands contained in internal registers or in main memory. First and second execution stage circuits are provided for executing the first and second instruction executing functions, respectively. The first execution stage circuit performs address calculation if the instruction involves main memory. The second execution stage circuit selects the appropriate operands and performs the arithmetic operation.

Abstract: A star local area network includes a ring bus hub (4) capable of being connected to a plurality of nodes (3, 5, 9) geographically distant from the hub by means of low speed serial links (18, 19, 21, 28). The nodes include processor means (2, 30, 31) for creating messages for transfer on the network. A plurality of duplex communication links (18, 19, 21, 28) connect the nodes to the ring bus hub (4). The hub (40) is comprised of a plurality of ring controllers (10, 12, 14, 16) driven by a common clock source (7). Each ring controller is connected by means of a number of parallel lines to other ring controllers in series to form a closed ring. Each one (3) of the plurality of nodes is geographically distant from the hub (4) and is connected to a corresponding one (10) of the ring controllers by means of one (18, 19) of the duplex communication links. The node controllers including node interface means (40) for transmitting the messages as a contiguous stream of words on the duplex communication link.

Abstract: In a communication system which is arranged to circulate an addressed electronic document among a plurality of terminals which are connected to one another through a transfer path and to sequentially add attest patterns indicative of the approvals of individual reviewing persons to the electronic document, a method for identifying the source of each person's approval symbol and amendments to the document. The data structure of each electronic document communicated between individual terminals is assembled in a data structure which separates the document content data from the attest patterns added to the document by the creating or reviewing person. If any reviewing person requests to amend the contents of the electronic document to which the attest patterns have been added, a display of only the content data of the above electronic document is presented to the reviewing person.

Abstract: A computer system operating under software control to provide output to a printer for printing. The computer system sets printer parameters to accommodate different forms of output to the printer. A word processing program stored in the computer memory is executed to couple information for printing to the printer with the printer in a first set of printer states. A typewriter emulator program stored in the computer memory is executable to couple information for printing to the printer and to set the printer states. The word processing program is interrupted by a hot key depressed by an operator, and the typewriter emulator program is entered, with the printer states being set in dependence upon printer state information for the typewriter emulator. When the typewriter emulator is interrupted by a hot key, the then-current printer states are stored and a set of default printer states for the word processor are restored prior to returning to execution of the word processing software.

Abstract: A system for emulating the operation of a terminal connected to a host computing system while retaining the ability to utilize personal computer application programs resident in the personal computer by utilizing a personal computer/host terminal emulation program which conducts an analysis of host data and keystrokes to identify personal computer commands and calls the appropriate resident application program in response to such commands.

Abstract: A method of operating a packet switching network is disclosed in which a Systems Network Architecture (SNA) computer can control a remote terminal cluster controller and terminals coupled thereto via a switched virtual circuit connection to the terminal cluster controller. The terminals coupled to the terminal cluster controller are able to establish switched virtual circuit connections to other compatible computers, independent of the computer by which the terminal cluster controller is controlled. This is achieved by an access module of the network, to which the terminal cluster controller is connected, presenting different representations of the terminal configuration to the different computers.

Abstract: A robotics-control processor for performing real-time inverse kinematics and inverse dynamics calculations involving three-dimensional vectors. The processor employs a three-wide register and execution unit architecture, pipelined instructions, and register-to-register data processing to achieve rapid vector calculations. Broadcast buffers for exchanging operands between register files, and operand multiplexing at several levels within the processor allow program operation flexibility. In a preferred embodiment, the processor includes a CORDIC algorithm unit for rapid vector rotation and trigonometric function calculations.

Abstract: A Fetch-Then-Confirm (FTC) policy is used for the handling of data fetch upon XIEX's in a tightly coupled multiprocessor environment. The fetch and/or use of a requested data line upon XIEX is allowed before the SCE receives the confirmation of validity (or invalidity) of the requested line through the clearing procedure. Whenever a line having uncertain validity is used by a CP the results of execution of instructions depending on the validity of the line should not be committed to the cache until a confirmation is received from the SCE. When the confirmation from the SCE indicates that a line L is known to be valid, all results depending on the validity of L can be processed as usual. If, however, the SCE indicates that a previously fetched line L having uncertain validity is in fact invalid, all operations performed based on L's contents should be aborted and restarted properly when a valid copy of L is received.

Abstract: Modularly Structured Digital Communications System having Operations-Oriented and Security-Oriented Components. The switching-oriented, the operations-oriented and the security-oriented components are divided into three structure levels such that apparatus program modules for generating logical switching technology messages, operating technology messages or security technology messages are provided in a line technology task structure. An operations-oriented coordination program module and switching procedure program modules for the control of the operations-oriented and of the switching-oriented information and data flow are provided in an operating technology switching technology coordination task structure. At least one operations-oriented and one security-oriented application program module for sequencing operations-oriented or security-oriented jobs are provided in an application task structure.

Abstract: A check memory stores the data to limit a range of terminal devices usable by operators and a range of items accessible by operators, such as files, data and application programs. When an operator operates a computer system, he enters his personal identification data to the computer system by a termainal device. A checker contained in the computer system checks if the operator specified by the entered personal identification data is authorized to use the terminal device, and if he is authorized to access the entered file. The check is performed based on the contents of the check memory. When he is authorized, the executed of the job is permitted. When he is not authorized, the execution of the job is prohibited. A personal data memory stores the data of his personnel administration and the data of his section in a company. When the section to which an operator has belonged is changed to another section, the personal data in the personal data memory is changed.

Abstract: A simplified bus interface circuit for stores applications includes on-chip pseudo-dual port memory that is user-configurable into receive and transmit portions that are further separable into blocks associated with various sets of commands by means of a pointer set of assignable pointers. The circuit provides for echo-back comparison of transmissions and confirmation, in the case of RT to RT commands that the correct terminal has initiated a message.

Abstract: A signal generator generates a temporal signal with a periodic configuration defined by an arrangement of seed patterns resulting from a branching construction iteratively using laws for composing several patterns and consisting in defining the periodic configuration of the signal as a component "a.sub.n " of the nth term Un with several components (a.sub.n, b.sub.n) of a recurrent sequence defined at the level of each of its components by a specific recurrent composition law, the initial term U0 having for its components the seed patterns (a.sub.0, b.sub.0). The temporal signals known as "fractal" signals result from a branching construction of this kind. The generator comprises a microprocessor (10) associated with a keyboard-display system (11), a read-only memory (12) for programs, a random access memory (13) and an output digital-to-analog converter (14).

Abstract: An information processing system comprises a high speed noninterlocked system bus 12 which couples together a plurality of system units including a main memory and a system bus interface (SBI) unit 34. The system bus interface unit is further coupled to an I/O bus 42 having a plurallity of I/O Processors 44, 46 coupled thereto. The system bus interface includes read and write buffer storage for buffering information units being transferred between the system bus and the I/O bus. The I/O bus includes two signal lines which differentiate the condition of an I/O bus SBI BUSY signal line. One of these two signal lines indicates when the SBI read buffer is full while the other signal line indicates when the SBI write buffer is full. The SBI Busy signal line indicates when either of these conditions exist. I/O processors are enabled to differentiate between read and write buffer full conditions, thereby effectively increasing the bandwidth of the I/O bus.