Abstract: A microprogram transfer register designation system for a microprogram controlled microprocessor which has a plurality of internal data buses such that there are previously prepared some number of source register sets each designating one source register for each of the internal buses and some number of destination register sets each designating one destination register for each of the internal buses, wherein one of the source register sets and one of the destination register sets is selected when an interregister transfer is executed. A transfer register designation field of a microcode includes at least one transfer inhibit flag for the internal buses.

Abstract: An arbitration system for a shared address, data and control bus provides burst mode operations for transferring data between a peripheral device and memory via a bus master. The arbitration system is responsive to high priority bus activities, such as memory refresh cycles and DMA cycles to temporarily transfer control of the shared bus from the bus master to a circuit controlling the high priority activity. After the high priority activity is completed, the arbitration system returns control of the shared bus to the bus master so that the associated peripheral device may continue operating in the burst mode. This transfer of control occurs without requiring the time overhead of arbitrating priority between bus masters having active bus requests. The arbitration system further includes timing circuits to assure that a bus master transferring data in the burst mode does not retain control of the shared bus for an excessive amount of time.

Abstract: A non-locking queueing mechanism is described for transferring information from a sending unit to a receiving unit through a queue in which there is no interference between the independent units (sender and receiver) during enqueueing or dequeueing. The invention thus avoids any form of interlock or serialism. The mechanism includes a first pointer (D), identifying the element area in the queueing device where the last dequeued information element, if any, was located, and a second pointer register for logging a second pointer (E) identifying the element area in the queueing device where the last enqueued information element, if any, was located, a first control block activated by the sending unit to enqueue the information element into the queueing device and for updating the second pointer, and a second control block activated by the recieving unit to dequeue the information element from the queueing device and for updating the first pointer.

Abstract: A buffer memory in a peripheral controller has dedicated page and word location segments for each one of a multiple number of attached peripheral units. Additionally, an auxiliary segment provides memory for the active status of each one of the multiple number of data transfer cycle operations which may be occurring concurrently and which status can be accessed at the optimum time so that each initiated data transfer cycle can be completed in a time-saving fashion. Memory address control means are provided for accessing page segments and word locations therein in order to insert data therein or to remove data therefrom. A special queue segment is available to provide concurrent status information for each I/O command initiated by a host computer.