Abstract: A high volume manufacturing (HVM) and circuit marginality validation (CMV) test for an integrated circuit (IC) is disclosed. The IC comprises a port binding and bubble logic in the front end to provide flexibility in binding a port to the uop and to create empty spaces (bubbles) in the uop flow. The out-of-order (OOO) cluster of the IC comprises reservation disable logic to control the flow sequence of the uops and stop schedule logic to temporarily stop dispatching the uops from the OOO cluster to the execution (EXE) cluster. The EXE cluster of the IC comprises signal event uops to generate fault information and fused uJump uops to specify combination of branch prediction, direction, and resolution in any portion of the test. Such features provide a tester the flexibility to perform HVM and CMV testing of the OOO and EXE clusters of the IC.

Abstract: Various aspects are disclosed herein for attenuating spin waiting in a virtual machine environment comprising a plurality of virtual machines and virtual processors. Selected virtual processors can be given time slice extensions in order to prevent such virtual processors from becoming de-scheduled (and hence causing other virtual processors to have to spin wait). Selected virtual processors can also be expressly scheduled so that they can be given higher priority to resources, resulting in reduced spin waits for other virtual processors waiting on such selected virtual processors. Finally, various spin wait detection techniques can be incorporated into the time slice extension and express scheduling mechanisms, in order to identify potential and existing spin waiting scenarios.

Abstract: A data processing apparatus comprises processing circuitry and a plurality of storage units. When the processing circuitry executes a data access instruction, then a storage controller identifies based on a target storage address of the data access instruction, which of the storage units includes the target storage location identified by the target storage address. Prediction circuitry is provided to predict a predicted storage unit predicted to include the target storage location, so that retrieval of the data value from the predicted storage unit can be initiated before the storage controller has identified the target storage unit. The prediction circuitry makes the prediction based on the type of the data access instruction executed by the processing circuitry.

Abstract: A data processing apparatus is disclosed, having: an instruction decoder configured to decode a stream of instructions, a data processor configured to process the decoded stream of instructions; wherein in response to a plurality of adjacent instructions within the stream of instructions execution of which is dependent upon a data condition being met and whose execution when said data condition is not met does not change a state of said processing apparatus, the processor is configured to: commence determining whether the data condition is met or not; and commence processing said plurality of adjacent instructions; and in response to determining that said data condition is not met; skip to a next instruction to be executed after said plurality of adjacent instructions without executing any intermediate ones of said plurality of adjacent instructions not yet executed and continue execution at the next instruction.

Abstract: An information processing apparatus includes an instruction supplying section that supplies a plurality of instructions as a single instruction group, an executing section that repetitively executes a plurality of execution processes corresponding to the plurality of instructions in parallel, an issue timing control section that controls an issue timing of each of the instructions to the executing section so that the plurality of execution processes are executed with a timing delayed in accordance with a predetermined latency, and an operand transforming section that transforms an operand register address of each of the instructions in accordance with a predetermined increment value upon every repetition of execution in the executing section.

Abstract: A method, apparatus and computer program product for performing efficient loop instruction execution using bit vector scanning is presented. A bit vector is scanned, each bit in the bit vector representing at least one of a feature and a conditional status. The presence of a bit of said bit vector set to a first state is detected. The bit is set to a second state. An instruction address for a routine corresponding to said bit set to a first state is looked up using a bit position of said bit that was set to a first state. The routine is executed. The scanning, said detecting, said setting and said using are repeated until there are no remaining bits of said bit vector set to said first state.

Abstract: A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first plurality of register files included in the central register file, and a plurality of shadow register files, each of the plurality of shadow register files corresponding to each of a third plurality of register files included in predetermined processing elements selected from the plurality of processing elements.

Abstract: In a processor having an instruction unit, a decode/issue unit, and execution queues configured to provide instructions to correspondingly different types execution units, a method comprises maintaining a duplicate free list for the execution queues. The duplicate free list includes a plurality of duplicate dependent instruction indicators that indicate when a duplicate instruction for a dependent instruction is stored in at least one of the execution queues. One of the duplicate dependent instruction indicators is assigned to an execution queue for a dependent instruction. The dependent instruction is executed only when the one of the duplicate dependent instruction indicators is reset.

Abstract: A method of extending a processor system within an integrated circuit (IC) can include executing program code within the processor system implemented within the IC, wherein the IC includes a programmable fabric. The processor system further can be coupled to the programmable fabric. A process can be performed using a process-specific circuit implemented within the programmable fabric in lieu of using the processor system. A result of the process from the process-specific circuit can be made available to the processor system.

Abstract: Store multiple instructions are managed based on previous execution history and their alignment. At least one store multiple instruction is detected. A flag is determined to be associated with the at least one store multiple instruction. The flag indicates that the at least one store multiple instruction has previously encountered an operand store compare hazard. The at least one store multiple instruction is organized into a set of unit of operations. The set of unit of operations is executed. The executing avoids the operand store compare hazard previously encountered by the at least one store multiple instruction.

Abstract: Mechanisms for performing all-to-all comparisons on architectures having limited storage space are provided. The mechanisms determine a number of data elements to be included in each set of data elements to be sent to each processing element of a data processing system, and perform a comparison operation on at least one set of data elements. The comparison operation comprises sending a first request to main memory for transfer of a first set of data elements into a local memory associated with the processing element and sending a second request to main memory for transfer of a second set of data elements into the local memory. A pair wise comparison computation of the all-to-all comparison of data elements operation is performed at approximately a same time as the second set of data elements is being transferred from main memory to the local memory.

Abstract: Various techniques for storing computer numbers such as floating-point numbers. In one embodiment, a data processing unit is configured to represent floating-point numbers using a first precision with a first number of bits and a second precision with a second number of bits, where the second number of bits is greater than the first number of bits. A floating-point type value may be set upon a memory store to indicate whether a first representation of a floating-point number uses the first or the second number of bits. A second representation of the floating-point number and the floating-point type value may be stored accordingly. In some embodiments, the second representation may correspond to the first representation with one or more bits shifted. This format may lead to memory power savings when reading from a memory location of the second precision when the result is indicated as the first precision.

Abstract: A single instruction multiple data processing pipeline 12 for processing floating point operands includes shared special case handling circuitry 34 for performing any operand dependent special case processing operations. The operand dependent special case processing operations result from special case conditions such as operands that are denormal, an infinity, a not-a-number and a floating point number requiring format conversion. The pipeline 12 may in some embodiments be stalled while the operands requiring special case processing are serially shifted to and from the shared special case handling circuitry 34. In other embodiments the instruction in which the special case condition for an operand arose may be recirculated through the pipeline with permutation circuitry 86, 94 being used to swap the operands between lanes in order to place the operand(s) requiring special case processing operations into the lane containing the shared special case handling circuitry 98.

Abstract: The described embodiments include a processor that executes a vector instruction. In the described embodiments, while dispatching instructions at runtime, the processor encounters a dependency-checking instruction. Upon determining that a result of the dependency-checking instruction is predictable, the processor dispatches a prediction micro-operation associated with the dependency-checking instruction, wherein the prediction micro-operation generates a predicted result vector for the dependency-checking instruction. The processor then executes the prediction micro-operation to generate the predicted result vector. In the described embodiments, when executing the prediction micro-operation to generate the predicted result vector, if a predicate vector is received, for each element of the predicted result vector for which the predicate vector is active, otherwise, for each element of the predicted result vector, the processor sets the element to zero.

Abstract: A system and method for issuing a processor instruction to multiple processing sections arranged in an out-of-order processing pipeline architecture. The multiple processing sections include a first execution unit with a pipeline length and a second execution unit operating upon data produced by the first execution unit. An instruction issue unit accepts a complex instruction that is cracked into respective micro-ops for the first execution unit and the second execution unit. The instruction issue unit issues the first micro-op to the first execution unit to produce intermediate data. The instruction issue unit then delays for a time period corresponding to the processing pipeline length of the first execution unit. After the delay, a second micro-op is issued to the second execution unit.

Abstract: Technologies are generally described herein for supporting program and data annotation for hardware customization and energy optimization. A code block to be annotated may be examined and a hardware customization may be determined to support a specified quality of service level for executing the code block with reduced energy expenditure. Annotations may be determined as associated with the determined hardware customization. An annotation may be provided to indicate using the hardware customization while executing the code block. Examining the code block may include one or more of performing a symbolic analysis, performing an empirical observation of an execution of the code block, performing a statistical analysis, or any combination thereof. A data block to be annotated may also be examined. One or more additional annotations to be associated with the data block may be determined.

Abstract: A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.

Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Abstract: The described embodiments provide a processor that executes vector instructions. In the described embodiments, while dispatching instructions at runtime, the processor encounters an Actual instruction. Upon determining that a result of the Actual instruction is predictable, the processor dispatches a prediction micro-operation associated with the Actual instruction, wherein the prediction micro-operation generates a predicted result vector for the Actual instruction. The processor then executes the prediction micro-operation to generate the predicted result vector. In the described embodiments, when executing the prediction micro-operation to generate the predicted result vector, if the predicate vector is received, for each element of the predicted result vector for which the predicate vector is active, otherwise, for each element of the predicted result vector, generating the predicted result vector comprises setting the element of the predicted result vector to true.

Abstract: A processor 4 is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered.