Abstract: The described embodiments provide a system for executing instructions in a processor. In the described embodiments, upon detecting a return of input data for a deferred instruction while executing instructions in an execute-ahead mode, the processor determines whether a replay bit is set in a corresponding entry for the returned input data in a miss buffer. If the replay bit is set, the processor transitions to a deferred-execution mode to execute deferred instructions. Otherwise, the processor continues to execute instructions in the execute-ahead mode.

Abstract: Embodiments of the invention broadly contemplate systems, methods, apparatuses and program products providing a power management technique for an HPC cluster with performance improvements for parallel applications. According to various embodiments of the invention, power usage of an HPC cluster is reduced by boosting the performance of one or more select nodes within the cluster so that the one or more nodes take less time to complete. Embodiments of the invention accomplish this by selectively identifying the appropriate node(s) (or core(s) within the appropriate node(s)) in the cluster and increasing the computing capacity of the selected node(s) (or core(s) within the appropriate node(s)).

Abstract: A data processing system and computer program product for processing instructions. The instructions are processed by a processor unit while using a first table in a plurality of tables to predict a set of instructions needed by the processor unit after processing of a conditional instruction. An identification is formed that a rate of success in correctly predicting the set of instructions when using the first table is less than a threshold number. A sequence of the instructions being processed by the processor unit is searched for an instruction that matches a marker in a set of markers for identifying when to use the plurality of tables. An identification that the instruction that matches the marker is formed. A second table from the plurality of tables referenced by the marker is identified. The second table is used in place of the first table.

Abstract: This application is concerned with a device and method for fetching instructions from a data store for processing by a data processor. The device comprises: a register for storing an address of an instruction to be processed by said data processor; a fetch unit responsive to an address input to said fetch unit to fetch an instruction stored at said address; an adder for adding a predetermined amount to said address stored in said register prior to sending said address to said fetch unit, said predetermined amount determining a position in a program flow said fetched instruction has with respect to said instruction addressed in said register; said adder being responsive to detection of a change in program flow to reset said predetermined amount to an initial value, and to increase said predetermined amount for subsequent fetches by an amount equal to the separation between addresses such that consecutive addresses are fetched up to a maximum predetermined amount.

Abstract: A system and method for fencing memory accesses. Memory loads can be fenced, or all memory access can be fenced. The system receives a fencing instruction that separates memory access instructions into older accesses and newer accesses. A buffer within the memory ordering unit is allocated to the instruction. The access instructions newer than the fencing instruction are stalled. The older access instructions are gradually retired. When all older memory accesses are retired, the fencing instruction is dispatched from the buffer.

Abstract: A load scheduler capable of limited issuing of out of order load instruction is disclosed. The load scheduler uses a max skipping threshold which limits the number of skipping load instructions and a max skipped threshold which limits the number of skipped load instructions. An address tag for a skipping instruction is stored in a skipping load instruction tracking unit when a skipping load instruction is issued. When a skipped load instruction issues, the address tag of the skipped load instruction is compared to the address tag of the skipping instruction to determine if a hazard from the out of order issuing of the skipping load instruction caused a hazard and must be flushed.

Abstract: Methods for storing branch information in an address table of a processor are disclosed. A processor of the disclosed embodiments may generally include an instruction fetch unit connected to an instruction cache, a branch execution unit, and an address table being connected to the instruction fetch unit and the branch execution unit. The address table may generally be adapted to store a plurality of entries with each entry of the address table being adapted to store a base address and a base instruction tag. In a further embodiment, the branch execution unit may be adapted to determine the address of a branch instruction having an instruction tag based on the base address and the base instruction tag of an entry of the address table associated with the instruction tag. In some embodiments, the address table may further be adapted to store branch information.

Abstract: A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).

Abstract: A method and a device having a plurality of bit operations capability, the device includes: a first and a second registers and an instruction fetch circuit, and an arithmetic logic unit adapted to: calculate, during a first clock cycle, a position value representative of a position, within a first information vector, of a first bit of information that has a first value; and to multiply the position value by a multiplication factor to provide a first result and to alter the value of the first bit to a second value to provide an updated information vector, during the first clock cycle.

Abstract: A processor includes an instruction unit which provides instructions for execution by the processor, a decode/issue unit which decodes instructions received from the instruction unit and issues the instructions, and a plurality of execution queues coupled to the decode/issue unit. Each issued instruction from the decode/issue unit is stored into an entry of at least one queue of the plurality of execution queues, wherein each entry of the plurality of execution queues is configured to store an issued instruction and a duplicate indicator corresponding to the issued instruction which indicates whether or not a duplicate instruction of the issued instruction is also stored in an entry of another queue of the plurality of execution queues.

Abstract: In response to a property of a conditional branch instruction associated with a loop, such as a property indicating that the branch is a loop-ending branch, a count of the number of iterations of the loop is maintained, and a multi-bit value indicative of the loop iteration count is stored in a Branch History Register (BHR). In one embodiment, the multi-bit value may comprise the actual loop count, in which case the number of bits is variable. In another embodiment, the number of bits is fixed (e.g., two) and loop iteration counts are mapped to one of a fixed number of multi-bit values (e.g., four) by comparison to thresholds. Separate iteration counts may be maintained for nested loops, and a multi-bit value stored in the BHR may indicate a loop iteration count of only an inner loop, only the outer loop, or both.

Abstract: The invention provides a processor comprising an execution unit for executing multiple threads, each thread comprising a sequence of instructions and each thread being designated to handle activity from at least one specified source. The processor also comprises a thread scheduler for scheduling a plurality of threads to be executed by the execution unit, said scheduling being based on the respective activity handled by the threads; and a plurality of sets of registers connected to the execution unit. Each set of registers is arranged to store information representing a respective one of the plurality of threads, at least a part of the information being accessible by the execution unit for use in executing the respective thread when scheduled.

Abstract: Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and d

Abstract: A request control device, request control method, and a multiprocessor cooperation architecture. The request control device is connected to a request storage module and includes a comparing means and an identifier means. The comparing means is configured to determine if an incoming first queue unit corresponds to the same message with a queue unit that has existed in the request storage module. The identifier setting means is configured to set a save identifier of the queue unit that has existed in the request storage module to indicate not to save a state associated with the message if the first queue unit corresponds to the same message with the queue unit that has existed in the request storage module. According to the technical solution of the invention, the access to the memory caused by saving/loading the states is reduced and thereby increases the processing speed of the processor.

Abstract: A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Abstract: The described embodiments provide a processor for generating a result vector with incremented or decremented values from an input vector. During operation, the processor receives an input vector and a control vector. The processor then copies a value contained in a selected element of the input vector. The processor next generates the result vector, which involves writing an incremented or decremented value to the result vector, depending on the value of the control vector and the embodiment. In addition, a predicate vector can be used to control the values that are written to the result vector.

Abstract: Systems and methods for performing single instruction multiple data (SIMD) operations on a data set. The methods may include examining a structure of the data set to determine what reorganization may be necessary to facilitate SIMD processing. The method may include selecting a stored bit mask corresponding to the organization of the data set and loading the bit mask into an application specific register (ASR). Subsequently, the data may be reorganized inline according to the ASR as the data is loaded into the SIMD functional unit such that the SIMD functional unit may operate on the data set. The results of the SIMD operation may be written to a results register.

Abstract: Source code to be processed is analyzed and configuration data in implementing in accordance with each of plural implementation systems is created and is stored in a local memory of a DRP incorporating system. When execution of target processing is started, the implementation system determination processing calculates estimated processing time when the configuration of each of the implementation systems is adopted and determines the optimum one of the implementation systems based on a combination of the estimated processing time and the circuit scale of the configuration.

Abstract: To provide a device to reconfigure multi-level logic networks, which enable logic modification and reconfiguration of a multi-level logic network with small circuit area and low-power dissipation in a simple manner. For example, in the case of reconfiguring a multi-level logic network following logic modification for deleting an output vector F(b) of an objective logic function F(X) corresponding to an input vector b, unmodified pq elements are selected one by one from the nearest pq element EG to an output side. At this time, among output values of pq elements closer to an input side than selected pq elements, output values corresponding to the input vector, which equal an output value corresponding to any input variable X other than the input vector b are considered modified and thus not selected. Then, a selected output value corresponding to the input vector b is rewritten to an “invalid value”.

Abstract: A method and system for providing a memory access check on a processor including the steps of detecting accesses to a memory device including level-1 cache using a wakeup unit. The method includes invalidating level-1 cache ranges corresponding to a guard page, and configuring a plurality of wakeup address compare (WAC) registers to allow access to selected WAC registers. The method selects one of the plurality of WAC registers, and sets up a WAC register related to the guard page. The method configures the wakeup unit to interrupt on access of the selected WAC register. The method detects access of the memory device using the wakeup unit when a guard page is violated. The method generates an interrupt to the core using the wakeup unit, and determines the source of the interrupt. The method detects the activated WAC registers assigned to the violated guard page, and initiates a response.