Abstract: The present invention is directed to a novel etching process for a semiconductor material which inhibits corrosion of metal comprised of pretreating the material, preferably with a surfactant, and then exposing the material to a mixture comprising salt, a buffered oxide etch, and optionally a surfactant.

Abstract: A method for providing a dielectric film having enhanced adhesion and stability. Pre-deposition, post deposition and post cure treatments enhance adhesion of the dielectric film to an underlying substrate and overlying cap layer. The enhanced film is particularly useful as an intermetal or premetal dielectric layer in an integrated circuit. A pre-deposition treatment process with atomic hydrogen enhances film adhesion by reducing weakly bound oxides on the surface of the substrate. A post-deposition densification process in a reducing atmosphere enhances stability if the film is to be cured ex-situ. In a preferred embodiment, the layer a low dielectric constant film deposited from a process gas of ozone and an organosilane precursor having at least one silicon-carbon (Si—C) bond.

Abstract: To move an article in and out of plasma during plasma processing, the article is rotated by a first drive around a first axis, and the first drive is itself rotated by a second drive. As a result, the article enters the plasma at different angles for different positions of the first axis. The plasma cross-section at the level at which the plasma contacts the article is asymmetric so that those points on the article that move at a greater linear velocity (due to being farther from the first axis) move longer distances through the plasma. As a result, the plasma processing time becomes more uniform for different points on the article surface. In some embodiments, two shuttles are provided for loading and unloading the plasma processing system. One of the shuttles stands empty waiting to unload the processed articles from the system, while the other shuttle holds unprocessed articles waiting to load them into the system.

Abstract: An etchant for patterning indium tin oxide, wherein the etchant is a mixed solution of HCl, CH3COOH, and water, and a method of fabricating a liquid crystal display device are disclosed in the present invention. The method includes forming a gate electrode on a substrate, forming a gate insulating layer and an amorphous silicon layer on the gate electrode including the substrate, forming an active area by patterning the amorphous silicon layer, forming a source electrode and a drain electrode on the active area, forming a passivation layer on the source electrode and the drain electrode and the gate insulating layer, forming a contact hole exposing a part of the drain electrode, forming an indium tin oxide layer on the passivation layer, and forming an indium tin oxide electrode by selectively etching the indium tin oxide layer using a mixed solution of HCl, CH3COOH, and water as an etchant.

Abstract: A polishing pad for use in polishing a surface of a substrate comprises a pad main body having a polishing surface and a plurality of electrode portions formed within the pad main body and mutually spaced apart in a plane direction of the pad main body. Each electrode portion is formed of a conductive portion and an insulating portion formed on the conductive portion.

Abstract: An etching apparatus has (a) a processing unit to ionize a reactive gas and generate plasma to process a semiconductor wafer, (b) a bed on which the semiconductor wafer is set, (c) a first magnet arranged below the semiconductor wafer in the vicinity of the periphery of a semiconductor chip forming area defined on the semiconductor wafer, and (d) a second magnet arranged above the semiconductor wafer in the vicinity of the periphery of the semiconductor chip forming area.

Abstract: Within a method for fabricating a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a blanket target layer. There is then formed over the blanket target layer a patterned mask layer. There is then measured, while employing an optical method, a linewidth of the patterned mask layer to determine a patterned mask layer measured linewidth. There is then determined a deviation of the patterned mask layer measured linewidth from a patterned mask layer target linewidth. There is then etched, while employing a plasma etch method, the blanket target layer to form a patterned target layer while employing the patterned mask layer as a etch mask layer.

Abstract: Plasma treating a low-k dielectric layer (104) using an oxidation reaction (e.g., O2) to improve patterning. Resist poisoning occurs due to an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The plasma treatment is performed to either pretreat a low-k dielectric (104) before forming the pattern (130, 132), during a rework of the pattern (130, 132), or between via and trench patterning to reduce resist poisoning.

Abstract: The temperature of the specimen holder 6 in the vacuum container 1 is lowered with the thermal control unit 11 to adjust the temperature of the specimen 7 composed of a silicon substrate to a low temperature of 0° C. or lower. Then, trenches are formed in the specimen 7 by plasma etching using an etching gas comprising SF6 as the main constituent and optionally O2 as an additive. Thus, the etching rate and the yield can be increased in the trench formation in the silicon semiconductor substrate.

Abstract: Methods and apparatus are provided for combining the manufacturing of a fixed-abrasive substrate and the chemical mechanical planarization of semiconductor wafers using a single process path.

Abstract: A semiconductor manufacturing process is disclosed that may form a contact structure with a tungsten plug. A contact structure hole may be adequately filled with tungsten, while avoiding plug loss, increased resistance and/or trenching, that can result from conventional approaches. According to one particular embodiment, a titanium film (003) may be deposited with an anisotropic sputtering method, such as an ion metal plasma method, or the like. A titanium film (003) may have a thickness outside a contact hole (020) that is 100 nm or more. However, due to anisotropic sputtering, a titanium film (003) within a contact hole (020) may be thinner than outside the contact hole (020). A contact hole (020) may then be filled with a tungsten film (005). A tungsten film (005) and titanium film (003) may then be etched back leaving a tungsten plug having shape with an upwardly projecting portion.

Abstract: A method for forming a semiconductor device comprises forming a first layer over a semiconductor substrate. At least one hole is formed through the first layer. A bottom anti-reflective coating (BARC) layer is formed in the at least one hole. A first heating is performed to heat the BARC layer to a flow temperature. A second heating is performed to heat the BARC layer to a hardening temperature so that the BARC layer hardens, wherein the hardening temperature is greater than the flow temperature. An etch is performed to form a trench in the first layer and over the at least one hole, wherein the hardened BARC layer in the at least one hole acts as an etch resistant layer during the etch. As an alternative to the second heating step, the BARC may be simply hardened. The first and second heating may be performed within a heating chamber without removing the semiconductor substrate.

Abstract: This invention relates to a method of forming a substrate with preparing a surface capable of making a cocontinuous bond comprising the steps of 1) obtaining a copper or copper alloy substrate and 2) applying an etching composition which comprises (a) an acid, (b) an oxidizing agent, (c) a copper complexing agent, and (d) a copper complex, wherein the copper complex is present in an amount which precipitates when applied to the copper or copper alloy substrate. The method also includes the step of 3) treating the substrate with a coating composition and/or 4) applying a stripping composition to the substrate. The invention also relates to copper articles, having surface porosity, including multilayer articles such as printed circuit boards and compositions used in the method. The present invention provides microporous copper or copper alloy substrates which have improved adhesion properties to organic material.

Abstract: A method of polishing a wafer in a carrier by a polishing pad, controlling a ratio of platen speed to carrier speed (PS to CS) within a specific range, or controlling a first polishing step with a PS to CS ratio in the range of about 150:1 to about 1:150 followed by a second polishing step with a platen speed of about 0 to 20 rpm while maintaining the carrier speed used in the first polishing step, which maximizes clearing of residual material removed from a patterned wafer surface by polishing.

Abstract: A method for detecting end-point in a plasma etching process by monitoring plasma impedance changes on a time scale is disclosed. In the method, a plasma etching process is first conducted in a process chamber, while changes in a parameter of plasma impedance in the chamber occurring during the etching process is recorded in a curve on a time scale. An end-point of the plasma etching process is then defined for the etching of a specific material layer at a point where the direction of a slope of the curve changes.

Abstract: Chemical mechanical polishing compositions and slurries comprising a film forming agent and at least one silane compound wherein the compositions are useful for polishing substrate features such as copper, tantalum, and tantalum nitride features.

Abstract: A chemical mechanical polishing slurry comprising a film forming agent, an oxidizer, a complexing agent and an abrasive, and a method for using the chemical mechanical polishing slurry to remove copper alloy, titanium, and titanium nitride containing layers from a substrate.

Abstract: A method of forming a dual damascene structure. A substrate having a conductive layer thereon is provided. A passivation layer, a first dielectric layer, an etching stop layer, a second dielectric layer and cap layer serving as a base anti-reflection coating are sequentially formed over the substrate. The cap layer and the second dielectric layer are patterned to form a first opening that exposes a portion of the etching stop layer. A patterned negative photoresist layer having a second opening therein is formed above the cap layer. The cap layer exposed by the second opening and the second dielectric layer exposed by the first opening are removed. Thereafter, the second dielectric layer exposed by the second opening is removed to form a trench and the first dielectric layer exposed by the first opening is removed to form a via opening. The passivation layer exposed by via opening and then the negative photoresist layer is removed.

Abstract: A method for checking the position of alignment marks after a chemical mechanical polishing (CMP) process and automatically compensating for alignment of a wafer stepper based on the position checking is described. A wafer is provided having an alignment mark thereon for the purpose of aligning a reticle in the wafer stepper. The wafer is polished by CMP. Thereafter, alignment mark positioning is checked for deviation from a normal vectorial position of the alignment mark whereby information about the deviation is fed back to the wafer stepper and wherein the wafer stepper automatically compensates for correctable alignment error based on the deviation information.

Abstract: A method of fabricating a semiconductor device causing no pattern shifting of a peripheral oxide film etc. in removal of both of an antireflection film and a mask pattern and having a fine structure not implementable solely by photolithography and the semiconductor device are obtained. The method of fabricating a semiconductor device comprises steps of forming a base film of either a silicon film or a silicon compound film on a semiconductor substrate, forming a hard film of either a metal film or a metal compound film on the base film, forming a resist pattern on the hard film, dryly etching the hard film through the resist pattern serving as a mask for forming a hard pattern, dryly etching the base film through the hard pattern serving as a mask and removing the hard pattern by wet etching with a chemical solution not etching at least the base film.