Abstract: A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than ?rd of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed.

Abstract: A method for forming a damascene structure to improve a chemical mechanical polishing (CMP) process while reducing the capacitance in an integrated circuit including forming a shallow dummy damascene adjacent active damascenes and removing the dummy damascene in a CMP process while forming the adjacent active damascenes.

Abstract: The present invention relates to a process for selectively plasma etching a structure upon a semiconductor substrate to form designated topographical structure thereon utilizing an undoped silicon dioxide layer as an etch stop. In one embodiment, a substantially undoped silicon dioxide layer is formed upon a layer of semiconductor material. A doped silicon dioxide layer is then formed upon said undoped silicon dioxide layer. The doped silicon dioxide layer is etched to create the topographical structure. The etch has a material removal rate that is at least 10 times higher for doped silicon dioxide than for undoped silicon dioxide or the semiconductor material. One application of the inventive process includes selectively plasma etching a multilayer structure to form a self-aligned contact between adjacent gate stacks and a novel gate structure resulting therefrom. In the application, a multilayer structure is first formed comprising layers of silicon, gate oxide, polysilicon, and tungsten silicide.

Abstract: A method for forming a metal interconnect comprises exposing a dielectric layer to an etch chemistry containing nitrogen-containing compound such as NH3, NF3 or N2O. The nitrogen-containing compound provides selectivity and/or profile control comparable to that provided by N2, while avoiding poisoning of photoresist by embedded N2.

Abstract: A method for anisotropic plasma etching of organic-containing insulating layers is disclosed. According to this method at least one opening is created in an organic-containing insulating layer formed on a substrate. These openings are created substantially without depositing etch residues by plasma etching said insulating layer in a reaction chamber containing a gaseous mixture which is composed such that the plasma etching is highly anisotropic. Examples of such gaseous mixtures are a gaseous mixture comprising a fluorine-containing gas and an inert gas, or a gaseous mixture comprising an oxygen-containing gas and an inert gas, or a gaseous mixture comprising HBr and an additive. The plasma etching of the organic-containing insulating layer can be performed using a patterned bilayer as an etch mask, said bilayer comprising a hard mask layer, being formed on said organic-containing insulating layer, and a resist layer being formed on said hard mask layer.

Abstract: A method and structure for an apparatus for removing metal from an integrated circuit structure is disclosed. A container holds an integrated circuit structure that has a metal portion. An electronic device connected to the container produces an electronic field proximate to a limited region of the metal portion. A first supply connected to the container supplies an oxidizing agent within the container. A solvent supply connected to the container supplies solvent to the limited region of the metal portion.

Abstract: According to one embodiment, a shallow trench isolation (STI) method (500) may include forming an etch mask layer over both a first and second substrate side (504). An etch mask layer over a first substrate side (506) may be patterned to form a STI etch mask, and trenches may be etched into a substrate (508). A trench dielectric layer can be formed over a first substrate side (510). An etch mask layer formed over a second substrate side can be etched (512), reducing and/or eliminating stress that may deform a substrate or otherwise adversely affect STI features. A trench dielectric may then be chemically-mechanically polished (step 514).

Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.

Abstract: Techniques for detecting endpoints during semiconductor dry-etching processes are described. The dry-etching process of the present invention involves using a combination of a reactive material and a charged particle beam, such as an electron beam. In another embodiment, a photon beam is used to facilitate the etching process. The endpoint detection techniques involve monitoring the emission levels of secondary electrons and backscatter electrons together with the current within the sample. Depending upon the weight given to each of these parameters, an endpoint is identified when the values of these parameters change more than a certain percentage, relative to an initial value for these values.

Abstract: A silicon oxide film having a ununiform thickness is deposited inside each of trenches defined in a silicon substrate by etching within a device isolation region, in such a manner that only corner portions of trench bottoms are exposed. The silicon substrate is selectively etched from the exposed trench corner portions of the silicon substrate lying inside the trenches to thereby increase the volume of each trench.

Abstract: Methods of etching dielectric materials in a semiconductor processing apparatus use a thick silicon upper electrode that can be operated at high power levels for an extended service life.

Abstract: A multi-step etching process for a lead overlay structure such as a thin-film magnetic head structure using secondary ion mass spectroscopy (SIMS) whereby high selectivity of a lead material or other high conductivity metal layer is realized versus that of a metallic mask material and stopping layer. The first step includes patterning the mask layer using IBE or RIE. Advantageously, a photoresist layer is present over a portion of the mask layer and is left in place to be removed in a subsequent step. The second step includes etching the high conductivity metal layer using CAIBE or RIBE with an inert/reactive gas mixture and using SIMS to detect when the stopping layer is reached.

Abstract: Planarizing machines and methods for selectively using abrasive slurries on fixed-abrasive planarizing pads in mechanical and/or chemical-mechanical planarization of microelectronic substrate assemblies. In one embodiment of a method in accordance with the invention, a microelectronic substrate is planarized by positioning a fixed-abrasive planarizing pad on a table of a planarizing machine, covering at least a portion of a planarizing surface on the pad with a first abrasive planarizing solution during a first stage of a planarizing cycle, and then adjusting a concentration of the abrasive particles on the planarizing surface at a second stage of the planarizing cycle after the first stage. The concentration of the second abrasive particles can be adjusted during the second stage of the planarizing cycle by coating the planarizing surface with a non-abrasive second planarizing solution without abrasive particles during the second stage.

Abstract: A fabrication method of a semiconductor device improved in the polishing rate of an insulation film and less likely to generate a defect during polishing is obtained. In this fabrication of a semiconductor device, impurities are introduced into a first insulation film, and then planarization is effected by polishing the surface of the first insulation film. Thus, the polishing rate of the portion of the first insulation film in which impurities are introduced is improved. Also a defect is not easily generated therein.

Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.

Abstract: The present invention is directed to a system, method and software product for creating a predictive model of the endpoint of etch processes using Partial Least Squares Discriminant Analysis (PLS-DA). Calibration data is collected from a calibration wafer using optical emission spectroscopy (OES). The data may be non-periodic or periodic with time and periodic signals may be sampled synchronously or non-synchronously. The OES data is arranged in a spectra matrix X having one row for each data sample. The OES data is processed depending upon whether or not it is synchronous. Synchronous data is arranged in an unfolded spectra matrix X having one row for each period of data samples. A previewed endpoint signal is plotted using wavelengths known to exhibit good endpoint characteristics. Regions of stable intensity values in the endpoint plot that are associated with either the etch region or the post-etch region are identified by sample number.

Abstract: Plasma etching or deposition is performed over substrates using spatially localized micro-plasmas operating in parallel with each other. A plasma generating electrode is positioned closely adjacent to an exposed surface of the substrate, as on the surface of a dielectric layer applied to the substrate. A selected pressure of the gas in the region of the electrode and the substrate is established, and a voltage is applied between the plasma generating electrode and the substrate or a second electrode to ignite a plasma in the region between the plasma generating electrode and the substrate for a selected period of time. This plasma is limited to the region of the plasma generating electrode adjacent to the exposed surface so that the substrate is plasma treated in a desired pattern.

Abstract: A provided method for manufacturing the semiconductor device includes the steps of: forming a trench in a silicon substrate on which a silicon oxide film and a silicon nitride film are sequentially stacked; oxidizing the silicon substrate by an oxidation method of not forming nearly at all a silicon oxide film on a surface of the silicon nitride film, to form a silicon oxide film on the surface of the trench and perform pullback etching on the silicon nitride film; and performing rounding oxidation by using radical oxidation to round an edge of the surface of the trench. Therefore, it is possible to perform pullback etching on the nitride film, even in case of performing rounding oxidation by using radical oxidation.

Abstract: A processing line includes a process tool, a metrology tool, a tool state monitor, and a sampling controller. The processing tool is configured to process workpieces. The metrology tool is configured to measure an output characteristic of selected workpieces in accordance with a sampling plan. The tool state monitor is configured to observe at least one tool state variable value during the processing of a selected workpiece in the processing tool. The sampling controller is configured to receive the observed tool state variable value and determine the sampling plan for the metrology tool based on the observed tool state variable value. A method for processing workpieces includes processing a plurality of workpieces in a processing tool. A characteristic of selected workpieces is measured in accordance with a sampling plan. At least one tool state variable value is observed during the processing of a particular workpiece in the processing tool.

Abstract: The invention provides a method for forming a capacitor that enables to form HSG-Si on the entire surface of the exposed surface of a cylindrical bottom electrode. A core pattern is formed on the cylinder core layer on a semiconductor substrate, and an amorphous silicon film is formed so as to cover the core pattern. The amorphous silicon film on the cylinder core layer is removed so that the amorphous silicon film remains on the inside wall of the core pattern, and a bottom electrode comprising the amorphous silicon film is formed on the inside wall of the core pattern. The cylinder core layer that is the component of the core pattern is etching-removed, and then the natural oxide film generated on the surface of the bottom electrode and the amorphous silicon surface layer that is the component of the bottom electrode is etching-removed. Thereafter, HSG-Si is formed on the surface of the bottom electrode.