Patents Examined by George R. Fourson
  • Hall element
    Patent number: 10333057
    Abstract: A hall element is provided to suppress fluctuation in a Hall output voltage of the hall element which is generated due to a fluctuation in stress. The hall element may be formed to include a substrate, a magnetosensitive portion formed on the substrate, an insulating film formed on the magnetosensitive portion, four conductive portions (electrode portions and contact portions) which are formed on the insulating film, electrically connected to the magnetosensitive portion through the insulating film, and disposed at positions serving as vertexes of a quadrangle, and ball portions electrically connected to the conductive portions, and at least one ball portion is disposed on a diagonal line of the quadrangle formed by a region surrounded by the four conductive portions and above a portion where the conductive portion and the insulating film are in contact with each other.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 25, 2019
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Tomoya Shoji, Tsuyoshi Akagi
  • Semiconductor device including an ultraviolet light receiving element and method of manufacturing the same
    Patent number: 10326029
    Abstract: First and second semiconductor light receiving elements each include: a first P-type semiconductor region which is formed in an N-type semiconductor substrate; a first N-type semiconductor layer region which is formed in the first P-type semiconductor region; a P-type semiconductor region having a high concentration which is formed in the first P-type semiconductor region; and an N-type semiconductor region having a high concentration which is formed in the first N-type semiconductor layer region. On the semiconductor substrate, insulating oxide films are formed. On the first and the second semiconductor light receiving elements, insulating oxide films that have different thicknesses are formed.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: June 18, 2019
    Assignee: ABLIC INC.
    Inventor: Takeshi Koyama
  • Common procedure of interconnecting electronic chip with connector body and forming the connector body
    Patent number: 10319620
    Abstract: A method which comprises applying a common pressing force operative to interconnect an electronic chip with a connector body by an interconnect structure, and to contribute to a forming of the connector body.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: June 11, 2019
    Assignee: Infineon Technologies AG
    Inventor: Stuart Cardwell
  • Quantum rod, quantum rod film and quantum rod display device including the same
    Patent number: 10319930
    Abstract: Embodiments relate to a quantum rod, a quantum rod film, a quantum rod display device with a quantum rod. The quantum rod includes a first core, a second core separated from the first core, and a first shell surrounding the first and second cores.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: June 11, 2019
    Assignees: LG DISPLAY CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Kyu-Nam Kim, So-Mang Kim, Duk-Young Jeon, Yong-Hee Lee
  • Semiconductor device gate spacer structures and methods thereof
    Patent number: 10312348
    Abstract: A semiconductor device includes a substrate having a channel region; a gate stack over the channel region; a seal spacer covering a sidewall of the gate stack, the seal spacer including silicon nitride; a gate spacer covering a sidewall of the seal spacer, the gate spacer including silicon oxide, the gate spacer having a first vertical portion and a first horizontal portion; and a first dielectric layer covering a sidewall of the gate spacer, the first dielectric layer including silicon nitride.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: June 4, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Chang Huang, Fu-Peng Lu, Chun-Chang Liu, Chen-Chiu Huang
  • Thermally enhanced semiconductor package having field effect transistors with back-gate feature
    Patent number: 10304753
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: May 28, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Semiconductor device and method for manufacturing semiconductor device
    Patent number: 10297490
    Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a plurality of short-circuit prevention-regions of a second conductivity type at an upper portion of the semiconductor substrate, a first insulating film on a top surface of the semiconductor substrate, a strip-shaped fuse on a top surface of the first insulating film spanning over the short-circuit prevention-regions, a second insulating film on a top surface of the fuse, and a passivation film on a top surface of the second insulating film and having an opening for laser trimming. The opening exposes the second insulating film above an area including the short-circuit prevention-regions.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: May 21, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Taichi Karino
  • Semiconductor memory device and structure
    Patent number: 10297599
    Abstract: A semiconductor device, including: a plurality of non-volatile memory cells including a first memory cell and a second memory cell, where the plurality of non-volatile memory cells includes source diffusion lines and drain diffusion lines, at least one of the source diffusion lines and drain diffusion lines are shared by the first memory cell and the second memory cell, where the first memory cell includes a thin tunneling oxide of less than 1 nm thickness, and where the second memory cell includes a thick tunneling oxide of greater than 2 nm thickness.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: May 21, 2019
    Assignee: MONOLITHIC 3D Inc.
    Inventors: Zvi Or-Bach, Jin-Woo Han
  • Semiconductor device, making method, and laminate
    Patent number: 10297485
    Abstract: A semiconductor device is provided comprising a support, an adhesive resin layer, an insulating layer, a redistribution layer, a chip layer, and a mold resin layer. The adhesive resin layer consists of a resin layer (A) comprising a photo-decomposable resin containing a fused ring in its main chain and a resin layer (B) comprising a non-silicone base thermoplastic resin and having a storage elastic modulus E? of 1-500 MPa at 25° C. and a tensile break strength of 5-50 MPa. The semiconductor device is easy to fabricate and has thermal process resistance, the support is easily separated, and a semiconductor package is efficiently produced.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: May 21, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Hiroyuki Yasuda, Michihiro Sugo, Hideto Kato, Kazunori Kondo
  • Device and method of dielectric layer
    Patent number: 10290739
    Abstract: A method includes etching a semiconductor substrate to form a trench extending from a top surface of the semiconductor substrate into the semiconductor substrate. A first liner layer is formed on sidewalls and a bottom of the trench. The trench is filled with a dielectric material after depositing the first liner layer. The dielectric material and the first liner layer include substantially the same metal-contained ternary dielectric material. Excess portions of the dielectric material and the first liner layer over the top surface of the semiconductor substrate are removed.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Yun Peng, Keng-Chu Lin
  • Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element
    Patent number: 10283565
    Abstract: A method of forming a semiconductor structure includes forming a plurality of vertical field-effect transistors (VFETs) disposed on a substrate and forming a plurality of resistive elements disposed over top surfaces of the VFETs. Each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell. The VFETs are arranged in two or more columns and two or more rows, wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region and wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate. Top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: May 7, 2019
    Assignee: International Business Machines Corporation
    Inventors: Peng Xu, Kangguo Cheng, Juntao Li, Choonghyun Lee
  • Display panel
    Patent number: 10274801
    Abstract: A display panel includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of sub-pixel electrodes, and a first common electrode layer. The plurality of first signal lines and the plurality of second signal lines define a plurality of pixel areas together. Each of the plurality of sub-pixel electrodes is disposed in one of the plurality of pixel areas. The first common electrode layer includes a plurality of first common electrodes electrically connected to each other. Each first common electrode includes a stem and a plurality of branches, and the plurality of branches is coupled to two sides of the stem and extends away from the stem. An orthogonal projection of each stem onto the substrate is located between two adjacent sub-pixel electrodes. Orthogonal projections of the branches onto the substrate at least correspond to one sub-pixel electrode.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: April 30, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yen-Hua Lo, Szu-Yen Lin, Hsin-Chun Huang, Ching-Sheng Cheng
  • Self-aligned gate caps with an inverted profile
    Patent number: 10276391
    Abstract: Structures for a field-effect transistor and methods of forming a structure for field-effect transistor. A gate structure includes a work function metal layer, a first conductor layer, and a second conductor layer arranged over the work function metal layer. The second conductor layer has a sidewall and a top surface, and the first conductor layer has a first section arranged between the second conductor layer and the work function metal layer and a second section arranged adjacent to a first portion of the sidewall of the second conductor layer. A dielectric cap is arranged on the gate structure. The dielectric cap has a first section arranged over the top surface of the second conductor layer and a second section arranged adjacent to a second portion of the sidewall of the second conductor layer.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: April 30, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Ruilong Xie, Laertis Economikos
  • Semiconductor apparatus, method of manufacturing the same, and equipment
    Patent number: 10269638
    Abstract: A semiconductor apparatus includes a semiconductor substrate having an upper surface on which a semiconductor element is disposed, a lower surface opposite to the upper surface, and a side surface connecting the upper surface and the lower surface. The side surface has a plurality of concavities that each extend along the edge of the upper surface and that are arranged in a direction intersecting with the upper surface and the lower surface, and a plurality of ridges that are each located at the boundary between adjacent two of the plurality of concavities. The plurality of concavities and the plurality of ridges are covered with an insulating film containing carbon and fluorine.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: April 23, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kunihiro Abe
  • Thermally enhanced semiconductor package having field effect transistors with back-gate feature
    Patent number: 10269680
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package having field effect transistors (FETs) with a back-gate feature. The thermally enhanced semiconductor package includes a first buried oxide (BOX) layer, a first epitaxial layer over the first BOX layer, a second BOX layer over the first epitaxial layer, a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain, a gate dielectric aligned over the channel, and a front-gate structure over the gate dielectric. Herein, a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel. A FET is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 23, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott
  • Laminated structure and spin modulation element
    Patent number: 10263181
    Abstract: To provide a laminated structure and a spin modulation element capable of stably modulating spin polarizability of a ferromagnetic material by an electric field. A laminated structure according to an embodiment includes: a ferromagnetic layer; and a multiferroic layer formed on one surface of the ferromagnetic layer, wherein the multiferroic layer includes a first region having a rhombohedral crystal structure formed on a surface side on the ferromagnetic layer side and a second region having a tetragonal crystal structure formed further inside than the first region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: April 16, 2019
    Assignee: TDK CORPORATION
    Inventors: Eiji Suzuki, Katsuyuki Nakada, Shogo Yonemura
  • LED module
    Patent number: 10211189
    Abstract: An LED module includes: a substrate having a main surface and a back surface which face in opposite directions from each other in a thickness direction; a first LED chip including a first electrode pad bonded to a surface facing the same direction as the main surface; a first wire having one end bonded to the first electrode pad; and a wiring pattern having a main surface electrode formed in the main surface, wherein the main surface electrode includes a first die pad portion which supports the first LED chip, and when viewed from the thickness direction, the first die pad portion includes a main pad portion to which the first LED chip is bonded and an auxiliary pad portion which protrudes from the main pad portion in a direction toward a position of the first electrode pad from the center position in the first LED chip.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: February 19, 2019
    Assignee: Rohm Co., Ltd.
    Inventor: Masahiko Kobayakawa
  • Process for making multi-gate transistors and resulting structures
    Patent number: 10177006
    Abstract: In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: January 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Su-Hao Liu, Tsan-Chun Wang, Liang-Yin Chen, Jing-Huei Huang, Lun-Kuang Tan, Huicheng Chang
  • Alloyed underlayer for microelectronic interconnects
    Patent number: 7435679
    Abstract: Apparatus and methods of fabricating a microelectronic interconnect having an underlayer which acts as both a barrier layer and a seed layer. The underlayer is formed by co-depositing a noble metal and a barrier material, such as a refractory metal, or formed during thermal post-treatment, such as thermal annealing, conducted after two separately depositing the noble metal and the barrier material, which are substantially soluble in one another. The use of a barrier material within the underlayer prevents the electromigration of the interconnect conductive material and the use of noble material within the underlayer allows for the direct plating of the interconnect conductive material.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: October 14, 2008
    Assignee: Intel Corporation
    Inventors: Steven W. Johnston, Juan E. Dominguez
  • Trench power MOSFET with reduced gate resistance
    Patent number: 7368353
    Abstract: A method for manufacturing a trench type power semiconductor device which includes process steps for forming proud gate electrodes in order to decrease the resistivity thereof.
    Type: Grant
    Filed: November 4, 2004
    Date of Patent: May 6, 2008
    Assignee: International Rectifier Corporation
    Inventors: Jianjun Cao, Paul Harvey, Dave Kent, Robert Montgomery, Hugo Burke, Kyle Spring