Abstract: A semiconductor device including a ferroelectric random access memory, which has a structure suitable for miniaturization and easy to manufacture, and having less restrictions on materials to be used, comprises a field effect transistor formed on a surface area of a semiconductor wafer, a trench ferroelectric capacitor formed in the semiconductor wafer in one source/drain of the field effect transistor, wherein one electrode thereof is connected to the source/drain, and a wiring formed in the semiconductor wafer and connected to the other electrode of the trench ferroelectric capacitor.

Abstract: A semiconductor device has an NMOS portion and a PMOS portion. A first stress layer overlies a first channel to provide a first stress type to the channel and a first modified stress layer is formed from a portion of the first stress layer overlying a second channel. A second stress layer providing a second stress type overlies the first modified stress layer and a second modified stress layer is formed from a portion of the second stress layer overlying the first stress layer.

Abstract: Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid phase epitaxy regrowth step is performed on a thin layer of desired thickness of the amorphized region, in order to activate the first dopant only in this thin layer. Subsequently, a second dopant is implanted in the remaining amorphous region at a second doping concentration. Subsequent annealing of the substrate activates the second dopant only in said remaining region, so a very abrupt transition between dopant characteristics of the thin layer with first dopant and the region with the second dopant is obtained.

Abstract: The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.

Abstract: Disclosed herein is a semiconductor device with high reliability which has TFT of adequate structure arranged according to the circuit performance required. The semiconductor has the driving circuit and the pixel portion on the same substrate. It is characterized in that the storage capacitance is formed between the first electrode formed on the same layer as the light blocking film and the second electrode formed from a semiconductor film of the same composition as the drain region, and the first base insulating film is removed at the part of the storage capacitance so that the second base insulating film is used as the dielectric of the storage capacitance. This structure provides a large storage capacitance in a small area.

Abstract: A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

Abstract: A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.

Abstract: A method of manufacturing a ferroelectric film capacitor includes forming a platinum film used as an electrode material over a whole surface of a silicon substrate, batch-etching the platinum film to form opposite electrodes that serve as a pair of capacitor electrodes, and embedding a ferroelectric film corresponding to a dielectric film of the capacitor into a portion interposed between the pair of opposite electrodes.

Abstract: Methods of fabricating semiconductor devices are provided. Transistors are provided on a semiconductor substrate. A first interlayer insulating layer is provided on the transistors. A second interlayer insulating layer is provided on the first interlayer insulating layer. The second interlayer insulating layer defines a trench such that at least a portion of an upper surface of the first interlayer insulating layer is exposed. A resistor pattern is provided in the trench such that the at least a portion of the resistor pattern contacts the exposed portion of the first interlayer insulating layer. Related methods are also provided.

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

Abstract: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

Abstract: A method of manufacturing a semiconductor wafer wherein a film is formed on a back surface of a starting semiconductor wafer formed with circuits in a front surface thereof.

Abstract: A capacitor structure which has generally pyramidal or stepped profile to prevent or reduce dielectric layer breakdown is disclosed. The capacitor structure includes a first conductive layer, at least one dielectric layer having a first area provided on the first conductive layer and a second conductive layer provided on the at least one dielectric layer. The second conductive layer has a second area which is less than the first area of the at least one dielectric layer. A method of fabricating a capacitor structure is also disclosed.

Abstract: A method for forming a recess. The method includes providing a substrate with two protrusions having a first side wall and a second side wall opposite to the first side wall disposed above the substrate, conformally forming a mask layer on the substrate and the protrusions, tilt implanting the mask layer with a first angle using a first implanting mask adjacent to the first side wall of the protrusions, tilt implanting the mask layer with a second angle using a second implanting mask adjacent to the second side wall of the protrusions, removing implanted portions of the mask layer to form a patterned mask layer, and etching the substrate using the patterned mask layer, thereby forming a recess, wherein distances from the recess to the two protrusions, respectively, are different.

Abstract: A method is provided for manufacturing a capacitor including the steps of forming a lower electrode on a substrate, forming an insulation film formed of a perovskite type metal oxide on the lower electrode, and forming an upper electrode on the insulation film. The step of forming the insulation film includes the steps of coating a dispersion liquid in which fine crystal powder of a second metal oxide of a perovskite type in a liquid containing a precursor compound of a first metal oxide of a perovskite type on the lower electrode, and performing a heat treatment of the dispersion liquid after coating.

Abstract: In accordance with the objectives of the invention a new method and structure is provided for the creation of a capacitor. A contact pad and a lower capacitor plate have been provided over a substrate. Under the first embodiment of the invention, a layer of etch stop material, serving as the capacitor dielectric is deposited after which a triple layer of passivation is created over a substrate. The compound passivation layer is first etched, using a fuse mask, to define and expose the capacitor dielectric and a fuse area after which the passivation layer is second etched to define and expose the contact pad. A layer of AlCu is then deposited, patterned and etched to create a capacitor upper plate and a contact interconnect over the contact pad. Under a second embodiment of the invention, a triple layer of passivation is created over a layer of etch stop material deposited over a substrate, a contact pad and a lower capacitor plate have been provided over the substrate.

Abstract: A low relative permittivity SiOx film excellent in heat resistance without using an alkali metal, fluorine, etc., a method for modifying an SiOx film to accomplish a further reduction of the relative permittivity of the low relative permittivity SiOx film and further to increase the insulating property, a highly reliable semiconductor device free from crack or peeling of the film by employing the low relative permittivity SiOx film as an interlayer insulating film for metal wirings, are provided. The low relative permittivity film is characterized in that it is made of a porous material, the major constituent of which is SiOx (where 1.8?X?1.0), and the relative permittivity at 1 MHz is at most 2.3.

Abstract: A method is described for producing thin semiconductor films on a substrate by contacting a substrate with a solution containing a metal salt, a source of a Group VIa element, and chelating agent, and a noble metal in its elemental form. The resulting semiconductor films are useful for electronic and photovoltaic applications.

Abstract: Cassettes for holding thin semiconductor wafers for safe handling are provided, along with an improved methodology for reducing the thickness of semiconductor wafers. Embodiments include a cassette for holding thin semiconductor wafers, having a plurality of sets of center and edge supports, the sets being spaced from each other a distance greater than a sag amount of the wafers. The thin wafers are supported in a predetermined reference plane, so that tools such as robots or automatic handlers can be programmed to pick them up without damaging them. In another embodiment, a double into single pitch wafer cassette is provided having a wafer entrance section with spacing twice as large between sets of edge supports as a conventional cassette, to accommodate the sag/warp of the thin wafers, and a “flattening section” which guides and flattens the wafers between opposing edge supports as they are pushed into the cassette, such that the wafers are held substantially planar.

Abstract: A method for making a semiconductor device is described. That method comprises forming a dielectric layer on a substrate, forming a trench within the dielectric layer, and forming a high-k gate dielectric layer within the trench. After forming a first metal layer on the high-k gate dielectric layer, a second metal layer is formed on the first metal layer. At least part of the second metal layer is removed from above the dielectric layer using a polishing step, and additional material is removed from above the dielectric layer using an etch step.